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1.发明授权Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction 失效用于静态时序分析的方法和计算机程序，具有延迟降低和时钟稳定性降低公开(公告)号：US07480881B2
公开(公告)日：2009-01-20
申请号：US11465662
申请日：2006-08-18
申请人： Alexander Tetelbaum , Ruben Molina , Subodh Bhike
发明人： Alexander Tetelbaum , Ruben Molina , Subodh Bhike
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.
摘要翻译： 用于静态时序分析的方法和计算机程序包括接收集成电路设计的两个角的最小和最大阶段延迟作为输入。 根据净时钟周期间隔T_clk，发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第一延迟降额系数的函数，从最小和最大级延迟计算用于设置定时检查的路径松弛 Y1。 根据发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第二延迟降额因子Y2的函数的最小和最大级延迟来计算用于保持定时检查的路径松弛。 产生用于设置定时检查和保持定时检查的路径松弛作为输出。
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2.发明申请METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY DE-RATING AND CLOCK CONSERVATISM REDUCTION 失效用于具有延迟评估和时钟保持减少的静态时序分析的方法和计算机程序公开(公告)号：US20080046848A1
公开(公告)日：2008-02-21
申请号：US11465662
申请日：2006-08-18
申请人： Alexander Tetelbaum , Ruben Molina , Subodh Bhike
发明人： Alexander Tetelbaum , Ruben Molina , Subodh Bhike
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.
摘要翻译： 用于静态时序分析的方法和计算机程序包括接收集成电路设计的两个角的最小和最大阶段延迟作为输入。 根据净时钟周期间隔T_clk，发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第一延迟降额系数的函数，从最小和最大级延迟计算用于设置定时检查的路径松弛 Y1。 根据发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第二延迟降额因子Y2的函数的最小和最大级延迟来计算用于保持定时检查的路径松弛。 产生用于设置定时检查和保持定时检查的路径松弛作为输出。
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