公开(公告)号：US07480881B2

公开(公告)日：2009-01-20

申请号：US11465662

申请日：2006-08-18

申请人： Alexander Tetelbaum ,  Ruben Molina ,  Subodh Bhike

发明人： Alexander Tetelbaum ,  Ruben Molina ,  Subodh Bhike

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.

摘要翻译： 用于静态时序分析的方法和计算机程序包括接收集成电路设计的两个角的最小和最大阶段延迟作为输入。 根据净时钟周期间隔T_clk，发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第一延迟降额系数的函数，从最小和最大级延迟计算用于设置定时检查的路径松弛 Y1。 根据发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第二延迟降额因子Y2的函数的最小和最大级延迟来计算用于保持定时检查的路径松弛。 产生用于设置定时检查和保持定时检查的路径松弛作为输出。

公开(公告)号：US20080046848A1

公开(公告)日：2008-02-21

申请号：US11465662

申请日：2006-08-18

申请人： Alexander Tetelbaum ,  Ruben Molina ,  Subodh Bhike

发明人： Alexander Tetelbaum ,  Ruben Molina ,  Subodh Bhike

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and computer program for static timing analysis includes receiving as input minimum and maximum stage delays for two corners of an integrated circuit design. A path slack for a setup timing check is calculated from the minimum and maximum stage delays as a function of net clock cycle interval T_clk, launch path delay T_LP, capture path delay T_CP, data path delay T_DP, and a first delay de-rating factor Y1. A path slack for a hold timing check is calculated from the minimum and maximum stage delays as a function of the launch path delay T_LP, the capture path delay T_CP, the data path delay T_DP, and a second delay de-rating factor Y2. The path slack calculated for the setup timing check and for the hold timing check is generated as output.

摘要翻译： 用于静态时序分析的方法和计算机程序包括接收集成电路设计的两个角的最小和最大阶段延迟作为输入。 根据净时钟周期间隔T_clk，发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第一延迟降额系数的函数，从最小和最大级延迟计算用于设置定时检查的路径松弛 Y1。 根据发射路径延迟T_LP，捕获路径延迟T_CP，数据路径延迟T_DP和第二延迟降额因子Y2的函数的最小和最大级延迟来计算用于保持定时检查的路径松弛。 产生用于设置定时检查和保持定时检查的路径松弛作为输出。

公开(公告)号：US07062737B2

公开(公告)日：2006-06-13

申请号：US10901841

申请日：2004-07-28

申请人： Alexander Tetelbaum ,  Ruben Molina

发明人： Alexander Tetelbaum ,  Ruben Molina

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

摘要翻译： 公开了一种用于在集成电路设计中自动修复串扰违规的方法和计算机程序，其包括以下步骤：（a）作为输入接收集成电路设计; （b）从集成电路设计执行初始单元放置和全局布线; （c）根据来自初始小区布局和全局路由的第一组规则识别具有串扰违规的网络; （d）执行详细路由，其包括为在步骤（c）中识别的网络提供串扰保护; （e）根据来自详细路由的第二组规则来识别具有串扰违规的网络; 和（f）执行附加详细路由，其包括为在步骤（e）中识别的网络提供串扰保护。

公开(公告)号：US20060026539A1

公开(公告)日：2006-02-02

申请号：US10901841

申请日：2004-07-28

申请人： Alexander Tetelbaum ,  Ruben Molina

发明人： Alexander Tetelbaum ,  Ruben Molina

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068

摘要： A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

公开(公告)号：US06948142B2

公开(公告)日：2005-09-20

申请号：US10453819

申请日：2003-06-02

申请人： Alexander Tetelbaum ,  Ruben Molina, Jr.

发明人： Alexander Tetelbaum ,  Ruben Molina, Jr.

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5045

摘要： A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed to calculate a skew correction and a net ramptime for the selected net. An injected crosstalk delay of the selected net is estimated from a net aggressor. A crosstalk protection scheme is selected for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.

摘要翻译： 一种保护集成电路的网络免受注入的串扰延迟的方法包括：在信号路径结构中接收合成的信号路径结构和所选择的网络的最大允许注入的串扰延迟的值。 分析信号路径结构，以计算所选网络的偏斜校正和净冲击时间。 从网络攻击者估计所选网络的注入串扰延迟。 为所选择的网络选择串扰保护方案以最小化集成电路的芯片面积，同时确保所选网络的注入的串扰延迟不超过最大可允许注入的串扰延迟的值。

公开(公告)号：US06810505B2

公开(公告)日：2004-10-26

申请号：US10192989

申请日：2002-07-10

申请人： Alexander Tetelbaum ,  Maad A. Al-Dabagh ,  Duc Van Huynh ,  Ruben Molina, Jr.

发明人： Alexander Tetelbaum ,  Maad A. Al-Dabagh ,  Duc Van Huynh ,  Ruben Molina, Jr.

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.

公开(公告)号：US06442737B1

公开(公告)日：2002-08-27

申请号：US09876736

申请日：2001-06-06

申请人： Alexander Tetelbaum ,  Ruben Molina, Jr.

发明人： Alexander Tetelbaum ,  Ruben Molina, Jr.

IPC分类号： G06F1750

CPC分类号： G06F1/10 ,  G06F17/505

摘要： The present invention has application to final balancing of an initial balanced clock tree. In one aspect of the invention, a minimum set of clock buffer delays is generated to reduce clock skew to within a selected skew limit for each level of a balanced clock tree. In one embodiment, the difference between the optimum delay and the clock buffer delay selected from the minimum set of clock buffer delays for each clock buffer in the balanced clock tree is less than or equal to the selected skew limit. In one such embodiment, a method of balancing a clock tree includes the steps of receiving as input a minimum buffer delay, a maximum level skew limit, and a selected skew limit; generating a minimum set of clock buffer delays for replacing at least one clock buffer in the balanced clock tree with a clock buffer delay selected from the minimum set of clock buffer delays such that the difference between the optimum delay and the clock buffer delay is less than or equal to the selected skew limit; and generating as output the minimum set of clock buffer delays.

摘要翻译： 本发明适用于初始平衡时钟树的最终平衡。 在本发明的一个方面中，产生最小的时钟缓冲器延迟集，以将时钟偏移减小到对于平衡时钟树的每个级别的选定的偏移极限。 在一个实施例中，从平衡时钟树中的每个时钟缓冲器的最小时钟缓冲器延迟选择的最佳延迟和时钟缓冲器延迟之间的差小于或等于所选择的偏移极限。 在一个这样的实施例中，平衡时钟树的方法包括以下步骤：接收最小缓冲器延迟，最大电平偏移极限和选择的偏移极限作为输入; 产生最小的一组时钟缓冲器延迟，用于从时钟缓冲器延迟的最小组中选择的时钟缓冲器延迟来替换平衡时钟树中的至少一个时钟缓冲器，使得最佳延迟和时钟缓冲器延迟之间的差小于 或等于所选择的歪斜限制; 并产生最小的时钟缓冲器延迟集合作为输出。

公开(公告)号：US20130080986A1

公开(公告)日：2013-03-28

申请号：US13246102

申请日：2011-09-27

申请人： Alexander Tetelbaum ,  Hyuk-Jong Yi

发明人： Alexander Tetelbaum ,  Hyuk-Jong Yi

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system for, and method of, performing static timing analysis. In one embodiment, the system includes: (1) a CVS tool configured to determine a cell-based voltage supply corresponding to each of a plurality of cells in an integrated circuit design and (2) an STA tool configured to derate the each of the cells based on the corresponding cell-based voltage supply.

摘要翻译： 执行静态时序分析的系统和方法。 在一个实施例中，该系统包括：（1）CVS工具，被配置为在集成电路设计中确定与多个单元中的每一个相对应的基于单元的电压供应;以及（2）STA工具，被配置为将 基于相应的基于电池的电源。

公开(公告)号：US20090282381A1

公开(公告)日：2009-11-12

申请号：US12248016

申请日：2008-10-08

申请人： Alexander Tetelbaum ,  Sreejit Chakravarty

发明人： Alexander Tetelbaum ,  Sreejit Chakravarty

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

摘要： An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.

摘要翻译： 用于优化集成电路（IC）中过程监视器（PM）的放置的电子设计自动化（EDA）工具和方法。 在一个实施例中，EDA工具包括：（1）关键路径/小区标识符，被配置为识别IC中的关键路径和关键小区，（2）候选PM位置标识符，其耦合到关键路径/小区标识符并且被配置为识别 一组PM的候选位置，（3）耦合到关键路径/小区标识符并被配置为将关键小区相关联以形成其簇的簇生成器和（4）耦合到候选PM位置标识符的PM布局优化器，以及 所述簇生成器并且被配置为通过在所述候选位置之中选择来将PM放置在每个所述簇内。

公开(公告)号：US20070079274A1

公开(公告)日：2007-04-05

申请号：US11244486

申请日：2005-10-05

申请人： Alexander Tetelbaum

发明人： Alexander Tetelbaum

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method of routing an integrated circuit design includes steps of receiving as input at least a portion of an integrated circuit design including at least two separate routing rules assigned to the same net for routing the integrated circuit design, formulating a single combined routing rule as a function of content of each of the separate routing rules, and generating as output the combined routing rule and a routing rule assignment that assigns the combined routing rule to the net.

摘要翻译： 路由集成电路设计的方法包括以下步骤：接收作为输入的集成电路设计的至少一部分，包括分配给同一网络的至少两个分离的路由规则以路由集成电路设计，制定单个组合路由规则作为 每个单独的路由规则的内容的功能，以及将组合路由规则和将组合路由规则分配给网络的路由规则分配生成输出。