公开(公告)号：US20100095339A1

公开(公告)日：2010-04-15

申请号：US12460976

申请日：2009-07-27

Applicant: Ludovic Rattin ,  Subrata Chatterjee ,  Vishal Jain ,  Nitin Khanna

Inventor： Ludovic Rattin ,  Subrata Chatterjee ,  Vishal Jain ,  Nitin Khanna

IPC: H04N7/173

CPC classification number: H04L12/2801 ,  H04L49/00 ,  H04L49/109

Abstract: The present disclosure discloses a digital communication between the between embedded cable modem (eCM) and embedded set-top box (eSTB) via a shared memory. The communication is carried out by packet transfer mechanism as per the protocol without adding any extra header overhead. The communication link is established between the eSTB and eCM mainly in layer 2 and partly in layer 1 according to an implementation of the OSI model. Further, eSTB is used as an eSAFE device coupled to eCM where the eCM and eSTB are considered to be placed on two SoCs with a separate CPU to each SoC (System-On-Chip) with a shared memory (via high speed data bus protocol). DMA (Direct Memory Access) engines are used to accelerate data transfer and to reduce load. DMA of only eCM, SoC is used to minimize hardware resources.

Abstract translation: 本公开公开了通过共享存储器在嵌入式电缆调制解调器（eCM）和嵌入式机顶盒（eSTB）之间的数字通信。 通过根据协议的分组传送机制进行通信，而不增加额外的头部开销。 根据OSI模型的实现，通信链路主要在第2层和第1层之间建立在eSTB和eCM之间。 此外，eSTB被用作耦合到eCM的eSAFE设备，其中eCM和eSTB被认为被放置在具有单独CPU的两个SoC上，每个SoC（片上系统）具有共享存储器（通过高速数据总线协议 ）。 DMA（直接存储器访问）引擎用于加速数据传输和减少负载。 仅使用eCM的DMA，SoC用于最小化硬件资源。

公开(公告)号：US08898716B2

公开(公告)日：2014-11-25

申请号：US12460976

申请日：2009-07-27

Applicant: Ludovic Rattin ,  Subrata Chatterjee ,  Vishal Jain ,  Nitin Khanna

Inventor： Ludovic Rattin ,  Subrata Chatterjee ,  Vishal Jain ,  Nitin Khanna

IPC: H04N7/173 ,  H04L12/28 ,  H04L12/933 ,  H04L12/931

CPC classification number: H04L12/2801 ,  H04L49/00 ,  H04L49/109

Abstract: The present disclosure discloses a digital communication between the embedded cable modem (eCM) and embedded set-top box (eSTB) via a shared memory. The communication is carried out by packet transfer mechanism as per the protocol without adding any extra header overhead. The communication link is established between the eSTB and eCM mainly in layer 2 and partly in layer 1 according to an implementation of the OSI model. Further, eSTB is used as an eSAFE device coupled to eCM where the eCM and eSTB are considered to be placed on two SoCs with a separate CPU to each SoC (System-On-Chip) with a shared memory (via high speed data bus protocol). DMA (Direct Memory Access) engines are used to accelerate data transfer and to reduce load. DMA of only eCM, SoC is used to minimize hardware resources.

Abstract translation: 本公开公开了通过共享存储器在嵌入式电缆调制解调器（eCM）和嵌入式机顶盒（eSTB）之间的数字通信。 通过根据协议的分组传送机制进行通信，而不增加额外的头部开销。 根据OSI模型的实现，通信链路主要在第2层和第1层之间建立在eSTB和eCM之间。 此外，eSTB被用作耦合到eCM的eSAFE设备，其中eCM和eSTB被认为被放置在具有单独CPU的两个SoC上，每个SoC（片上系统）具有共享存储器（通过高速数据总线协议 ）。 DMA（直接存储器访问）引擎用于加速数据传输和减少负载。 仅使用eCM的DMA，SoC用于最小化硬件资源。

公开(公告)号：US20060209989A1

公开(公告)日：2006-09-21

申请号：US11254069

申请日：2005-10-19

Applicant: Kaushik Saha ,  Chiranjib Chakraborty ,  Subrata Chatterjee

Inventor： Kaushik Saha ,  Chiranjib Chakraborty ,  Subrata Chatterjee

IPC: H04L27/00

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs. The controlled clock period difference computation element is coupled at its output to the error correction device to form a feedback circuit to minimize error between the system clock output and successive PCR differences.

公开(公告)号：US07489742B2

公开(公告)日：2009-02-10

申请号：US11254069

申请日：2005-10-19

Applicant: Kaushik Saha ,  Chiranjib Chakraborty ,  Subrata Chatterjee

Inventor： Kaushik Saha ,  Chiranjib Chakraborty ,  Subrata Chatterjee

IPC: H04L27/00

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs. The controlled clock period difference computation element is coupled at its output to the error correction device to form a feedback circuit to minimize error between the system clock output and successive PCR differences.

Abstract translation: 一种用于数字视频通信中的时钟恢复的系统包括用于产生PCR输入信号并连续地确定连续PCR输入信号之间的时间间隔的延迟测量块。 该系统还包括：第一存储装置，用于产生对应于连续PCR输入信号到达之间的时间间隔的第一PCR信号和PCR到达间时间计算滤波装置，以确定连续PCR分组之间的平均到达时间差。 所述系统还包括用于使连续的PCR分组之间的平均PCR差异的误差最小化的纠错装置，耦合到纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于生成第一系统时钟的第二存储装置 输出和用于计算第一和第二系统时钟输出之间的时钟周期差的受控时钟周期差计算元件。 受控时钟周期差计算元件在其输出端耦合到纠错装置以形成反馈电路，以最小化系统时钟输出和连续PCR差异之间的误差。