公开(公告)号：US08543963B2

公开(公告)日：2013-09-24

申请号：US12695545

申请日：2010-01-28

申请人： Mahesh A. Iyer ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

摘要翻译： 一些实施例提供用于优化电路设计的全局泄漏功率的技术和系统。 在操作期间，系统可以确定电路设计中的逻辑门的泄漏电位，使得逻辑门的泄漏电位指示逻辑门的泄漏功率可以减小的量或程度。 然后，系统可以至少基于泄漏电位来确定用于处理逻辑门的处理顺序。 接下来，系统可以通过根据处理顺序尝试降低逻辑门的泄漏功率来优化电路设计的漏电功率。

公开(公告)号：US20110185334A1

公开(公告)日：2011-07-28

申请号：US12695556

申请日：2010-01-28

申请人： Mahesh A. Iyer ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.

摘要翻译： 泄漏功率优化系统优化包括一组逻辑门的电路设计的漏电功率。 系统为逻辑门选择泄漏功率降低转换，并确定逻辑门周围的区域。 该区域包括在逻辑门的扇出，逻辑门的扇入中的第一预定数量级内的逻辑门和逻辑门的扇出扇出中的第二预定数量的级。 系统传播区域内的到达时间，以在区域的端点获得更新的松弛值。 然后，响应于确定区域端点处的更新的松弛值不降低一个或多个电路定时度量，系统将泄漏功率降低变换应用于逻辑门。

公开(公告)号：US20110185333A1

公开(公告)日：2011-07-28

申请号：US12695545

申请日：2010-01-28

申请人： Mahesh A. Iyer ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

摘要翻译： 一些实施例提供用于优化电路设计的全局泄漏功率的技术和系统。 在操作期间，系统可以确定电路设计中的逻辑门的泄漏电位，使得逻辑门的泄漏电位指示逻辑门的泄漏功率可以减小的量或程度。 然后，系统可以至少基于泄漏电位来确定用于处理逻辑门的处理顺序。 接下来，系统可以通过根据处理顺序尝试降低逻辑门的泄漏功率来优化电路设计的漏电功率。

公开(公告)号：US08316339B2

公开(公告)日：2012-11-20

申请号：US12695556

申请日：2010-01-28

申请人： Mahesh A. Iyer ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.

摘要翻译： 泄漏功率优化系统优化包括一组逻辑门的电路设计的漏电功率。 系统为逻辑门选择泄漏功率降低转换，并确定逻辑门周围的区域。 该区域包括在逻辑门的扇出，逻辑门的扇入中的第一预定数量级内的逻辑门和逻辑门的扇出扇出中的第二预定数量的电平。 系统传播区域内的到达时间，以在区域的端点获得更新的松弛值。 然后，响应于确定区域端点处的更新的松弛值不降低一个或多个电路定时度量，系统将泄漏功率降低变换应用于逻辑门。

公开(公告)号：US08621408B2

公开(公告)日：2013-12-31

申请号：US13438602

申请日：2012-04-03

申请人： Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

摘要翻译： 描述了用于优化电路设计的系统和技术。 一些实施例减少库中的门数（例如，通过动态修剪库），这被考虑用于优化。 一些实施例创建线性延迟模型，并且使用线性延迟模型而不是非线性延迟模型来基本上减少检查特定替换门是否改善电路设计的一个或多个度量所需的计算量。 一些实施例确定用于处理库中的门或用于处理门的输入引脚的顺序，以便于早期拒绝门库中的候选门。 在一些实施例中，候选门转换的影响的评估逐渐地逐级地逐级地进行，直到门转换降级一个或多个度量为止。

公开(公告)号：US20130145336A1

公开(公告)日：2013-06-06

申请号：US13438602

申请日：2012-04-03

申请人： Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Robert Walker ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/84

摘要： Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics.

摘要翻译： 描述了用于优化电路设计的系统和技术。 一些实施例减少库中的门数（例如，通过动态修剪库），这被考虑用于优化。 一些实施例创建线性延迟模型，并且使用线性延迟模型而不是非线性延迟模型来基本上减少检查特定替换门是否改善电路设计的一个或多个度量所需的计算量。 一些实施例确定用于处理库中的门或用于处理门的输入引脚的顺序，以便于早期拒绝门库中的候选门。 在一些实施例中，候选门转换的影响的评估逐渐地逐级地逐级地进行，直到门转换降级一个或多个度量为止。