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公开(公告)号：US20110179392A1
公开(公告)日：2011-07-21
申请号：US13069411
申请日：2011-03-23
IPC分类号： G06F17/50
CPC分类号： H01L23/528 , H01L21/7684 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.
摘要翻译： 提供了一种用于确定互连线的布局的方法，包括：为所述互连线提供所需的宽度; 确定所述互连线的布局，包括切开所述互连线以提供沿着所述互连线延伸的两个或更多个手指，所述两个或更多个指状物与分隔相邻手指的细长狭槽; 以及通过将所需宽度与固体金属特征的最大宽度进行比较，以及最小的细长孔宽度来确定要布置在互连线的宽度上的多个细长孔。 两个或更多个手指和细长槽可以具有恒定的宽度并且跨越互连线宽度等间隔。 该方法可以包括选择手指的数量和槽的宽度以优化给定层技术的布局。
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公开(公告)号：US5790835A
公开(公告)日：1998-08-04
申请号：US582838
申请日：1996-01-02
CPC分类号： G06F17/5036
摘要： A system and method is provided for that allows the introduction of small sections of idealized conductive elements to be placed along a transmission line. The output is a partitioned transmission line whose segments between the idealized conductive elements are analyzed via circuit simulators as a distributed parasitic network, as opposed to the widely used lumped parasitic elements approach for the entire line. The distributed parasitic network system and method provides circuit designers with a parasitic extraction tool which allows the designer to define a transmission line segment for analysis, and create sub-networks of parasitic elements across the transmission line. These elements can then be passed to existing vendor circuit simulators for parasitic analysis, the result of which are more accurate than that derived using existing extraction tools whose output is limited to only a lumped parasitic parameter along the line.
摘要翻译： 提供了一种系统和方法，其允许引入沿着传输线放置的理想化导电元件的小部分。 输出是分布式传输线，其理想化导电元件之间的分段通过电路模拟器分析为分布式寄生网络，与广泛使用的整个线路的集总寄生元件方法相反。 分布式寄生网络系统和方法为电路设计人员提供了寄生提取工具，允许设计者定义用于分析的传输线段，并在传输线上创建寄生元件的子网络。 然后可以将这些元件传递给现有供应商电路模拟器用于寄生分析，其结果比使用现有提取工具得到的结果更准确，其输出仅限于沿线的集总寄生参数。
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公开(公告)号：US08943456B2
公开(公告)日：2015-01-27
申请号：US13069411
申请日：2011-03-23
IPC分类号： G06F17/50 , H01L23/528 , H01L21/768 , H01L23/522
CPC分类号： H01L23/528 , H01L21/7684 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.
摘要翻译： 提供了一种用于确定互连线的布局的方法，包括：为所述互连线提供所需的宽度; 确定所述互连线的布局，包括切开所述互连线以提供沿着所述互连线延伸的两个或更多个手指，所述两个或更多个指状物与分隔相邻手指的细长狭槽; 以及通过将所需宽度与固体金属特征的最大宽度进行比较，以及最小的细长孔宽度来确定要布置在互连线的宽度上的多个细长孔。 两个或更多个手指和细长槽可以具有恒定的宽度并且跨越互连线宽度等间隔。 该方法可以包括选择手指的数量和槽的宽度以优化给定层技术的布局。
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