Hardware based parallel processing cores with multiple threads and multiple pipeline stages
    1.
    发明授权
    Hardware based parallel processing cores with multiple threads and multiple pipeline stages 有权
    基于硬件的并行处理核心,具有多个线程和多个流水线阶段

    公开(公告)号:US08059650B2

    公开(公告)日:2011-11-15

    申请号:US11932656

    申请日:2007-10-31

    IPC分类号: H04L12/28

    CPC分类号: H04L49/3009

    摘要: A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.

    摘要翻译: 用于处理网络设备中数据包的流水线无序处理和系统。 流程和系统是可扩展的,以支持超过10 Gbps的吞吐量。 该系统包括一组处理核心,从中央处理单元卸载表查找操作和类似操作。 中央处理单元从一组处理核心接收对数据包进行转发,路由,NAT,防火墙维护和类似操作所需的必要数据。

    Providing desired service policies to subscribers accessing internet
    2.
    发明授权
    Providing desired service policies to subscribers accessing internet 有权
    为接入互联网的用户提供所需的服务策略

    公开(公告)号:US06952728B1

    公开(公告)日:2005-10-04

    申请号:US09600054

    申请日:1999-12-01

    IPC分类号: G06F15/173 H04L12/28

    CPC分类号: H04L12/2876 H04L12/2856

    摘要: An internet service node (ISN) enabling the provision of desired service policies to each subscriber. The ISN may contain multiple processor groups, with each subscriber being assigned to a processor group. The assigned processor group may be configured with the processing rules, which provide the service policies desired, by a subscriber. A port may determine the specific processor group to which received data is to be forwarded. A content addressable memory with masks for individual locations may be implemented to quickly determines the processor group to which received data is to be assigned to. Due to the features of the present invention, an ISN may be able to serve a large number of subscribers efficiently. The ISN may be used at the edge of an access network.

    摘要翻译: 互联网服务节点(ISN)能够为每个用户提供期望的服务策略。 ISN可以包含多个处理器组,每个用户被分配给处理器组。 分配的处理器组可以配置有由订户提供期望的服务策略的处理规则。 端口可以​​确定要向其转发接收到的数据的特定处理器组。 可以实现具有用于各个位置的掩码的内容可寻址存储器,以快速确定要被分配到哪个接收数据的处理器组。 由于本发明的特征,ISN可以有效地服务于大量用户。 ISN可以在接入网络的边缘使用。

    Backward compatibility for plug and play systems
    3.
    发明授权
    Backward compatibility for plug and play systems 失效
    即插即用系统的向后兼容性

    公开(公告)号:US5634075A

    公开(公告)日:1997-05-27

    申请号:US371304

    申请日:1995-01-11

    IPC分类号: G06F9/445 G06F12/06 G06F13/00

    CPC分类号: G06F9/4411 G06F12/0646

    摘要: A device for use in a computer system, particularly a personal computer (PC) which provides compatibility for a proposed ISA plug and play (PNP) standard. The device of the present invention is also backward compatible with non-PNP (legacy) PCs. Upon power-up, a device may initialize using default traditional or specification (ISA) values for I/O address, IRQ and DMA channels. If PNP activity by the host PC is detected by the device, the device is disabled, and awaits activation and I/O address, IRQ and DMA channel assignments from a host PC. If no PNP activity by a host PC is detected, the device continues to operate using default traditional or specification (ISA) I/O address, IRQ and DMA channels. The device of the present invention may be installed in PNP or legacy type PCs without reconfiguring hardware (e.g., DIP switches, jumpers or the like) in the device or installing new firmware, operating system, or applications software in a host PC.

    摘要翻译: 一种用于计算机系统中的装置,特别是为所提出的ISA即插即用(PNP)标准提供兼容性的个人计算机(PC)。 本发明的设备也向后兼容非PNP(传统)PC。 上电时,设备可以使用I / O地址,IRQ和DMA通道的默认传统或规范(ISA)值进行初始化。 如果设备检测到主机PC的PNP活动,则该设备被禁用,并且等待主机PC的激活和I / O地址,IRQ和DMA通道分配。 如果没有检测到主机PC的PNP活动,设备将使用默认的传统或规范(ISA)I / O地址,IRQ和DMA通道继续运​​行。 本发明的设备可以安装在PNP或传统型PC中,而不重新配置设备中的硬件(例如,DIP开关,跳线等)或在主机PC中安装新的固件,操作系统或应用软件。

    Hardware Based Parallel Processing Cores with Multiple Threads and Multiple Pipeline Stages
    4.
    发明申请
    Hardware Based Parallel Processing Cores with Multiple Threads and Multiple Pipeline Stages 有权
    具有多个线程和多个管道阶段的基于硬件的并行处理核心

    公开(公告)号:US20090109974A1

    公开(公告)日:2009-04-30

    申请号:US11932656

    申请日:2007-10-31

    IPC分类号: H04L12/56 H04L12/28

    CPC分类号: H04L49/3009

    摘要: A pipelined out-of-order process and system for handling data packets in a network device. The process and system are scalable to support throughput in excess of 10 Gbps. The system includes a set of processing cores that offload the table look up operations and similar operations from the central processing unit. The central processing unit receives the requisite data needed for performing forwarding, routing, NAT, firewall maintenance and similar operation on data packets from the set of processing cores.

    摘要翻译: 用于处理网络设备中数据包的流水线无序处理和系统。 流程和系统是可扩展的,以支持超过10 Gbps的吞吐量。 该系统包括一组处理核心,从中央处理单元卸载表查找操作和类似操作。 中央处理单元从一组处理核心接收对数据包进行转发,路由,NAT,防火墙维护和类似操作所需的必要数据。