公开(公告)号：US20120218847A1

公开(公告)日：2012-08-30

申请号：US13465982

申请日：2012-05-07

申请人： Jungtae KWON ,  David KIM ,  Sunil BHARDWAJ

发明人： Jungtae KWON ,  David KIM ,  Sunil BHARDWAJ

IPC分类号： G11C7/06

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4097 ,  G11C16/32 ,  G11C16/3418

摘要： Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

摘要翻译： 公开了用于减少半导体存储器件中的干扰的技术。 在一个特定的示例性实施例中，这些技术可以被实现为具有减小的干扰的半导体存储器件。 半导体存储器件可以包括以行和列的阵列排列的多个存储器单元。 半导体存储器件还可以包括耦合到多个存储器单元的多个数据读出放大器，被配置为在操作/访问周期期间执行一个或多个操作，其中操作/访问周期可以包括操作段和扰动 恢复部分。

公开(公告)号：US20110122687A1

公开(公告)日：2011-05-26

申请号：US12624856

申请日：2009-11-24

申请人： Jungtae Kwon ,  David Kim ,  Sunil Bhardwaj

发明人： Jungtae Kwon ,  David Kim ,  Sunil Bhardwaj

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C16/34

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4097 ,  G11C16/32 ,  G11C16/3418

摘要： Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

摘要翻译： 公开了用于减少半导体存储器件中的干扰的技术。 在一个特定的示例性实施例中，这些技术可以被实现为具有减小的干扰的半导体存储器件。 半导体存储器件可以包括以行和列的阵列排列的多个存储器单元。 半导体存储器件还可以包括耦合到多个存储器单元的多个数据读出放大器，被配置为在操作/访问周期期间执行一个或多个操作，其中操作/访问周期可以包括操作段和扰动 恢复部分。

公开(公告)号：US08699289B2

公开(公告)日：2014-04-15

申请号：US13465982

申请日：2012-05-07

申请人： Jungtae Kwon ,  David Kim ,  Sunil Bhardwaj

发明人： Jungtae Kwon ,  David Kim ,  Sunil Bhardwaj

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4097 ,  G11C16/32 ,  G11C16/3418

摘要： Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

公开(公告)号：US08174881B2

公开(公告)日：2012-05-08

申请号：US12624856

申请日：2009-11-24

申请人： Jungtae Kwon ,  David Kim ,  Sunil Bhardwaj

发明人： Jungtae Kwon ,  David Kim ,  Sunil Bhardwaj

IPC分类号： G11C11/34

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/08 ,  G11C7/18 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4091 ,  G11C11/4097 ,  G11C16/32 ,  G11C16/3418

摘要： Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

摘要翻译： 公开了用于减少半导体存储器件中的干扰的技术。 在一个特定的示例性实施例中，技术可以被实现为具有减小的干扰的半导体存储器件。 半导体存储器件可以包括以行和列的阵列排列的多个存储器单元。 半导体存储器件还可以包括耦合到多个存储器单元的多个数据读出放大器，被配置为在操作/访问周期期间执行一个或多个操作，其中操作/访问周期可以包括操作段和扰动 恢复部分。