公开(公告)号：US5802349A

公开(公告)日：1998-09-01

申请号：US589240

申请日：1996-01-22

Applicant: Dana M. Rigg ,  Sleiman Chamoun ,  James H. Tolar, II ,  Mark Chase ,  Supamas Sirichotiyakul

Inventor： Dana M. Rigg ,  Sleiman Chamoun ,  James H. Tolar, II ,  Mark Chase ,  Supamas Sirichotiyakul

IPC: G06F17/50 ,  G06F9/455

CPC classification number: G06F17/5045 ,  G06F17/5022

Abstract: A cell library (21) is optimized for specific operating characteristics. A stimulus file (23) is divided into a number of simulation run files. The simulation run files (27) are distributed to more than one computer work station so that the simulation of the cell occurs in parallel. The netlist (24) of each cell is parameterized to allow the cell to be changed and resimulated to better meet the specific operating characteristics. A cost function (32) is provided which uses the results of a transistor level simulation to calculate the quality of the cell design relative to the specific operating characteristics. Simulated annealing (34) is used to generate new simulation parameter values from a cost generated from the cost function (32). The cell is resimulated a number of times to optimize for the specific operating characteristics and the best design is retained for a new cell library (39). The process is repeated for each cell of the cell library (21).

Abstract translation: 细胞库（21）针对特定的操作特征进行了优化。 刺激文件（23）被分成多个模拟运行文件。 仿真运行文件（27）分布到多个计算机工作站，以便并行进行单元的仿真。 参数化每个单元的网表（24），以允许单元被改变和重新模拟以更好地满足特定的操作特性。 提供了一种成本函数（32），其使用晶体管级仿真的结果来计算相对于特定操作特性的单元设计的质量。 模拟退火（34）用于从成本函数（32）生成的成本生成新的模拟参数值。 细胞被重新刺激多次，以针对特定的操作特征进行优化，并为新的细胞库保留最佳设计（39）。 对细胞库（21）的每个细胞重复该过程。

公开(公告)号：US07149674B1

公开(公告)日：2006-12-12

申请号：US09580854

申请日：2000-05-30

Applicant: Supamas Sirichotiyakul ,  David T. Blaauw ,  Timothy J. Edwards ,  Chanhee Oh ,  Rajendran V. Panda ,  Judah L. Adelman ,  David Moshe ,  Abhijit Dharchoudhury

Inventor： Supamas Sirichotiyakul ,  David T. Blaauw ,  Timothy J. Edwards ,  Chanhee Oh ,  Rajendran V. Panda ,  Judah L. Adelman ,  David Moshe ,  Abhijit Dharchoudhury

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5022

Abstract: A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.

Abstract translation: 公开了一种提高双电位集成电路性能的方法，其中针对具有第一阈值电压电平的集成电路的每个晶体管计算第一值。 第一个值至少部分地基于如同对应的晶体管具有第二阈值电压电平那样计算的延迟和泄漏。 然后基于第一值选择一个晶体管。 然后将所选择的晶体管的阈值电压设置为第二阈值电压电平。 电路内的至少一个晶体管的面积被修改，然后将电路的尺寸设定到预定区域。 如果电路性能不能满足规定的约束，则可以重复该过程。 在一个实施例中，性能确定包括计算电路被分配到其中的一组DC连接组件的漏电流，确定每个组件的主要逻辑状态，估计这些主要逻辑状态中的每一个的泄漏，以及求和 基于状态概率的这些主成分的加权平均值。

公开(公告)号：US06799153B1

公开(公告)日：2004-09-28

申请号：US09553271

申请日：2000-04-20

Applicant: Supamas Sirichotiyakul ,  David T. Blaauw ,  Chanhee Oh ,  Vladimir P. Zolotov ,  Rafi Levy

Inventor： Supamas Sirichotiyakul ,  David T. Blaauw ,  Chanhee Oh ,  Vladimir P. Zolotov ,  Rafi Levy

IPC: G06F1750

CPC classification number: G06F17/5036 ,  G06F17/5031

Abstract: A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor. Accurate delay characterization provides for design engineers an accurate description of the worst case and best case scenarios of the integrated circuit or microprocessor that is needed for various applications such as the integration of the integrated circuit and microprocessor into a larger system.

Abstract translation: 对集成电路和其他微处理器应用执行交叉耦合延迟特性的解决方案。 本发明在各种时间适当地对各种配置的集成电路建模，以适应与驱动器电路相关联的非线性以及集成电路内的网络之间的不期望的电容耦合，特别是那些位于彼此非常接近并且产生有害的 司机过渡的影响从低到高，从高到低。 本发明提供了一种计算上有效的解决方案来执行微处理器内各个转换操作的加速和减慢的延迟表征。 精确的延迟表征为设计工程师提供了对于各种应用所需的集成电路或微处理器的最坏情况和最佳情况的精确描述，例如将集成电路和微处理器集成到更大的系统中。