公开(公告)号：US20160301413A1

公开(公告)日：2016-10-13

申请号：US14684372

申请日：2015-04-11

Applicant: Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

Inventor： Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

IPC: H03K19/094 ,  G01R31/3177

CPC classification number: H03K19/094 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2224/49113 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/13091

Abstract: An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.

Abstract translation: 本发明的实施例是用于生成识别号码（ID）的识别电路。 识别电路包括多个识别单元，每个识别单元包括具有彼此相对的第一输出和第二输出的锁存器。 第一输出和第二输出是识别电路的过程变化的函数。 第一缓冲器和第二缓冲器分别设置在锁存器的两侧并分别连接到锁存器的第一输出端和第二输出端。

公开(公告)号：US20170366185A1

公开(公告)日：2017-12-21

申请号：US15675705

申请日：2017-08-12

Applicant: Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

Inventor： Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

IPC: H03K19/094 ,  H01L23/544

CPC classification number: H03K19/094 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2224/49113 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/13091

Abstract: An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.

公开(公告)号：US09768781B2

公开(公告)日：2017-09-19

申请号：US14684372

申请日：2015-04-11

Applicant: Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

Inventor： Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

IPC: H01L23/544 ,  H03K19/094

CPC classification number: H03K19/094 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2224/49113 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/13091

Abstract: An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.

公开(公告)号：US09941886B2

公开(公告)日：2018-04-10

申请号：US15675705

申请日：2017-08-12

Applicant: Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

Inventor： Jimmy Yong Xiao ,  Surendra Kumar Rathaur ,  Visvamohan Yegnashankaran

IPC: H03K19/094 ,  H01L23/544

CPC classification number: H03K19/094 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2224/49113 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/13091

Abstract: An embodiment of the present invention is an identification circuit for generating an identification number (ID). The identification circuit includes a plurality of identification cells each comprising a latch having a first output and a second output that are opposite to each other. The first output and the second output are a function of process variations of the identification circuit. A first buffer and a second buffer are provided on both sides of the latch and connected to the first output and the second output of the latch, respectively.