公开(公告)号：US20100010798A1

公开(公告)日：2010-01-14

申请号：US12217793

申请日：2008-07-09

申请人： Vineet Wason ,  Sushant Suryagandh ,  Zhi-Yuan Wu ,  Priyanka Chiney ,  Niraj Subba

发明人： Vineet Wason ,  Sushant Suryagandh ,  Zhi-Yuan Wu ,  Priyanka Chiney ,  Niraj Subba

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, a voltage is applied to the gate terminal, a voltage is applied to the drain, and an electrical potential is applied between the gate terminal and gate. The magnitude of electrical potential applied between the gate terminal and gate is varied in proportion to the magnitude of voltage applied to the drain.

摘要翻译： 本方法是在晶体管模型中对漏极诱导的栅极降低（DIBL）建模的方法，晶体管模型基于MOSFET晶体管。 晶体管模型包括基极，源极，漏极，栅极和栅极端子。 在本方法中，向栅极端子施加电压，向漏极施加电压，并且在栅极端子与栅极之间施加电位。 施加在栅极端子和栅极之间的电位的大小与施加到漏极的电压的大小成比例地变化。

公开(公告)号：US20100207175A1

公开(公告)日：2010-08-19

申请号：US12371846

申请日：2009-02-16

申请人： Sushant SURYAGANDH ,  Ciby THURUTHIYIL ,  Kaveri MATHUR

发明人： Sushant SURYAGANDH ,  Ciby THURUTHIYIL ,  Kaveri MATHUR

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78654

摘要： A semiconductor transistor device is provided. The transistor device includes a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, and a drain region in the layer of semiconductor material. The source region has a stress-inducing semiconductor material located therein, while the drain region is free of any stress-inducing semiconductor material. This asymmetric arrangement of stress-inducing elements results in relatively high source-body leakage, and relatively low drain-body leakage, which is beneficial in analog circuit applications.

摘要翻译： 提供一种半导体晶体管器件。 晶体管器件包括半导体材料层，覆盖半导体材料层的栅极结构，半导体材料层中的源极区域和半导体材料层中的漏极区域。 源极区域具有位于其中的应力诱导半导体材料，而漏极区域没有任何应力诱导半导体材料。 应力诱导元件的这种不对称布置导致相对较高的源体泄漏以及相对低的漏极体泄漏，这在模拟电路应用中是有益的。