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公开(公告)号：US20100010798A1
公开(公告)日：2010-01-14
申请号：US12217793
申请日：2008-07-09
申请人： Vineet Wason , Sushant Suryagandh , Zhi-Yuan Wu , Priyanka Chiney , Niraj Subba
发明人： Vineet Wason , Sushant Suryagandh , Zhi-Yuan Wu , Priyanka Chiney , Niraj Subba
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, a voltage is applied to the gate terminal, a voltage is applied to the drain, and an electrical potential is applied between the gate terminal and gate. The magnitude of electrical potential applied between the gate terminal and gate is varied in proportion to the magnitude of voltage applied to the drain.
摘要翻译： 本方法是在晶体管模型中对漏极诱导的栅极降低（DIBL）建模的方法，晶体管模型基于MOSFET晶体管。 晶体管模型包括基极，源极，漏极，栅极和栅极端子。 在本方法中，向栅极端子施加电压，向漏极施加电压，并且在栅极端子与栅极之间施加电位。 施加在栅极端子和栅极之间的电位的大小与施加到漏极的电压的大小成比例地变化。
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公开(公告)号：US20090259453A1
公开(公告)日：2009-10-15
申请号：US12082533
申请日：2008-04-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of modeling an SRAM cell is provided. Initially, transistor models are provided based on transistor devices, and an SRAM cell model is provided including the transistor models. The present methodology streamlines the modeling process by modeling in order the pull up, pass gate and pull down transistors so as to minimize the number of transistor modeling iterations needed, and by focusing on the specific areas of transistor operation to achieve the desired level of operational accuracy. Variations to the model are provided, mimicking variations in data from actual devices, and yield based on failure estimation is measured using the model and its variations.
摘要翻译： 提供了一种对SRAM单元进行建模的方法。 最初，基于晶体管器件提供晶体管模型，并且提供包括晶体管模型的SRAM单元模型。 本方法通过对上拉，通过栅极和下拉晶体管进行建模来简化建模过程，以最小化所需的晶体管建模迭代次数，并通过专注于晶体管操作的特定区域来实现所需的操作水平 准确性。 提供了模型的变化，模拟来自实际设备的数据的变化，并且使用模型及其变化来测量基于故障估计的产量。
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