公开(公告)号：US06707718B1

公开(公告)日：2004-03-16

申请号：US10200539

申请日：2002-07-22

申请人： Azrul Halim ,  Colin Bill ,  Ken Cheong Cheah ,  Syahrizal Salleh

发明人： Azrul Halim ,  Colin Bill ,  Ken Cheong Cheah ,  Syahrizal Salleh

IPC分类号： G11C1606

CPC分类号： G11C29/44 ,  G11C16/04 ,  G11C29/16 ,  G11C29/48

摘要： For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node. The first resistor and the second resistor form a resistive voltage divider at the output node between the high voltage source and the low voltage source when the first transistor and the second transistor are turned on. A logic circuit turns on the first transistor and the second transistor when a first set of control signals indicate that program margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. The first transistor, the second transistor, the first resistor, the second resistor, and the logic circuit are fabricated on the semiconductor wafer. In another embodiment of the present invention, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source for erase margining of the CAM cell.

摘要翻译： 为了产生用于偏置制造在半导体晶片上的闪存器件的CAM（内容可寻址存储器）单元的栅极的裕度电压，高电压源设置有制造在半导体晶片上的电压发生器。 从耦合到制造在半导体晶片上的电压发生器的节点提供低电压源。 例如，用于提供高电压源的电压发生器包括在半导体晶片上制造的电压调节器和电荷泵，而低电压源是接地节点。 此外，第一晶体管耦合到高电压源，第二晶体管耦合到低电压源。 第一电阻器耦合在第一晶体管和输出节点之间，第二电阻耦合在第二晶体管和输出节点之间。 在输出节点产生裕度电压。 当第一晶体管和第二晶体管导通时，第一电阻器和第二电阻器在高电压源和低电压源之间的输出节点处形成电阻分压器。 当第一组控制信号指示在BIST（内置自测试）模式期间CAM单元的编程余量被调用时，逻辑电路接通第一晶体管和第二晶体管。 在半导体晶片上制造第一晶体管，第二晶体管，第一电阻器，第二电阻器和逻辑电路。 在本发明的另一个实施例中，逻辑电路关闭第一晶体管并导通第二晶体管，使得输出节点放电到低电压源的电压以消除CAM单元的擦除裕度。

公开(公告)号：US06973003B1

公开(公告)日：2005-12-06

申请号：US10677073

申请日：2003-10-01

申请人： Syahrizal Salleh ,  Edward V. Bautista, Jr. ,  Ken Cheong Cheah

发明人： Syahrizal Salleh ,  Edward V. Bautista, Jr. ,  Ken Cheong Cheah

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40622 ,  G11C11/406

摘要： A memory device and a method for refreshing the memory device. The memory device includes a memory cell capable of storing two bits of data. One bit is referred to as the normal data bit and the other bit is referred to as the complementary data bit. Each memory cell has an associated dynamic reference cell. The normal data is refreshed by latching refresh data into a data latch and ORing the latched data with input data. The refresh data is written to the corresponding memory location. The data for the complementary data bit is refreshed by latching complementary data bit refresh data into the complementary data latches and writing to the memory cell. The normal and complementary data bits are refreshed before each read operation.

摘要翻译： 一种用于刷新存储器件的存储器件和方法。 存储器件包括能够存储两位数据的存储器单元。 一位被称为正常数据位，另一位称为互补数据位。 每个存储单元具有相关联的动态参考单元。 正常数据通过将刷新数据锁存到数据锁存器中并将锁存数据与输入数据进行OR运算来刷新。 刷新数据被写入相应的存储单元。 通过将互补数据位刷新数据锁存到互补数据锁存器中并写入存储单元来刷新补充数据位的数据。 正常和互补的数据位在每次读取操作之前刷新。