公开(公告)号：US06884712B2

公开(公告)日：2005-04-26

申请号：US10359975

申请日：2003-02-07

申请人： Pradeep Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Zhen Jia Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

发明人： Pradeep Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Zhen Jia Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6656

摘要： An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

摘要翻译： 提供了一种集成电路及其制造方法。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

公开(公告)号：US08304834B2

公开(公告)日：2012-11-06

申请号：US11466350

申请日：2006-08-22

申请人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

发明人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

IPC分类号： H01L27/12

CPC分类号： H01L21/76895 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

公开(公告)号：US20060281253A1

公开(公告)日：2006-12-14

申请号：US11466350

申请日：2006-08-22

申请人： Pradeep Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

发明人： Pradeep Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76895 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

公开(公告)号：US07119005B2

公开(公告)日：2006-10-10

申请号：US11045202

申请日：2005-01-27

申请人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

发明人： Pradeep Ramachandramurthy Yelehanka ,  Tong Qing Chen ,  Zhi Yong Han ,  Jia Zhen Zheng ,  Kelvin Ong ,  Tian Hao Gu ,  Syn Kean Cheah

IPC分类号： H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6656

摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。