公开(公告)号：US20060018174A1

公开(公告)日：2006-01-26

申请号：US11169241

申请日：2005-06-27

申请人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

发明人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

公开(公告)号：US20100265780A1

公开(公告)日：2010-10-21

申请号：US12762620

申请日：2010-04-19

申请人： Taek-Seon PARK ,  Reum OH

发明人： Taek-Seon PARK ,  Reum OH

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C11/4076 ,  G11C8/18 ,  G11C2207/2272

摘要： A semiconductor memory device comprises a latency delay unit that toggles a delay clock signal on during a first interval between a time point where read burst signal is activated and a time point where a latency signal is activated, and subsequently toggling the delay clock signal on during a second interval between a time point where the read burst signal is inactivated and a time point where the latency signal is inactivated.

摘要翻译： 一种半导体存储器件包括等待延迟单元，其在读取脉冲串信号被激活的时间点和等待时间信号被激活的时间点之间的第一间隔期间切换延迟时钟信号，随后在延迟时间信号期间触发延迟时钟信号 读取脉冲串信号被去激活的时间点与等待时间信号被去激活的时间点之间的第二间隔。

公开(公告)号：US07164615B2

公开(公告)日：2007-01-16

申请号：US11169241

申请日：2005-06-27

申请人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

发明人： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

公开(公告)号：US07590010B2

公开(公告)日：2009-09-15

申请号：US12006682

申请日：2008-01-04

申请人： Taek-Seon Park ,  Sung-Min Yim

发明人： Taek-Seon Park ,  Sung-Min Yim

IPC分类号： G11C7/10

CPC分类号： G11C7/06 ,  G11C7/1051 ,  G11C7/1069

摘要： A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data. The second latch is for latching the amplified differential data to generate second latched data having an opposite phase from the amplified differential data. The amplified differential data from outputs of the sense amplifier are applied substantially simultaneously to inputs of the first and second latches.

摘要翻译： 数据输出电路包括读出放大器和第一和第二锁存器。 读出放大器用于放大差分数据以产生放大的差分数据。 第一锁存器用于锁存放大的差分数据以产生具有与放大差分数据相同相位的第一锁存数据。 第二锁存器用于锁存放大的差分数据以产生具有与放大的差分数据相反的相位的第二锁存数据。 来自读出放大器的输出的经放大的差分数据基本上同时施加到第一和第二锁存器的输入。

公开(公告)号：US20080170452A1

公开(公告)日：2008-07-17

申请号：US12006682

申请日：2008-01-04

申请人： Taek-Seon Park ,  Sung-Min Yim

发明人： Taek-Seon Park ,  Sung-Min Yim

IPC分类号： G11C7/06

CPC分类号： G11C7/06 ,  G11C7/1051 ,  G11C7/1069

摘要： A data output circuit includes a sense amplifier and first and second latches. The sense amplifier is for amplifying differential data to generate amplified differential data. The first latch is for latching the amplified differential data to generate first latched data having a same phase as the amplified differential data. The second latch is for latching the amplified differential data to generate second latched data having an opposite phase from the amplified differential data. The amplified differential data from outputs of the sense amplifier are applied substantially simultaneously to inputs of the first and second latches.

摘要翻译： 数据输出电路包括读出放大器和第一和第二锁存器。 读出放大器用于放大差分数据以产生放大的差分数据。 第一锁存器用于锁存放大的差分数据以产生具有与放大差分数据相同相位的第一锁存数据。 第二锁存器用于锁存放大的差分数据以产生具有与放大的差分数据相反的相位的第二锁存数据。 来自读出放大器的输出的经放大的差分数据基本上同时施加到第一和第二锁存器的输入。

公开(公告)号：US08228748B2

公开(公告)日：2012-07-24

申请号：US12762620

申请日：2010-04-19

申请人： Taek-Seon Park ,  Reum Oh

发明人： Taek-Seon Park ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C8/18 ,  G11C2207/2272

摘要： A semiconductor memory device comprises a latency delay unit that toggles a delay clock signal on during a first interval between a time point where read burst signal is activated and a time point where a latency signal is activated, and subsequently toggling the delay clock signal on during a second interval between a time point where the read burst signal is inactivated and a time point where the latency signal is inactivated.

摘要翻译： 一种半导体存储器件包括等待延迟单元，其在读取脉冲串信号被激活的时间点和等待时间信号被激活的时间点之间的第一间隔期间切换延迟时钟信号，随后在延迟时间信号期间触发延迟时钟信号 读取脉冲串信号被去激活的时间点与等待时间信号被去激活的时间点之间的第二间隔。