公开(公告)号：US20240184467A1

公开(公告)日：2024-06-06

申请号：US18444215

申请日：2024-02-16

Applicant: Lodestar Licensing Group LLC

Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/1045 ,  G11C2207/2272

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

公开(公告)号：US11914888B2

公开(公告)日：2024-02-27

申请号：US17852165

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  G06F2213/16 ,  G11C7/1015 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L2225/06541

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US11715504B2

公开(公告)日：2023-08-01

申请号：US17518888

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong Kim ,  Tae-young Oh ,  Kyung-soo Ha

IPC: G11C7/22 ,  G11C8/18 ,  G11C29/50 ,  G11C7/10 ,  G11C8/10 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C8/10 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C7/1072 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US11710527B2

公开(公告)日：2023-07-25

申请号：US17868685

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Qisong Lin ,  Shane Nowell ,  Mustafa N. Kaynak

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C29/00 ,  G06F11/07 ,  G11C16/26 ,  G06F3/06 ,  G11C16/04

CPC classification number: G11C16/34 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/84 ,  G11C16/0483 ,  G11C2207/229 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

公开(公告)号：US20190213136A1

公开(公告)日：2019-07-11

申请号：US16359514

申请日：2019-03-20

Applicant: Everspin Technologies, Inc.

Inventor： Thomas S. ANDRE ,  Syed M. ALAM ,  Chitra K. SUBRAMANIAN ,  Javed S. BARKATULLAH

IPC: G06F12/0893 ,  G06F3/06 ,  G06F12/0862 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C11/16 ,  G06F12/02 ,  G06F12/0802

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US20190171272A1

公开(公告)日：2019-06-06

申请号：US16193247

申请日：2018-11-16

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G06F1/3234 ,  G06F5/06 ,  G06F1/3287 ,  G11C11/4093

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US20190101975A1

公开(公告)日：2019-04-04

申请号：US16205356

申请日：2018-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G06F3/00 ,  G11C7/10 ,  G11C11/4063 ,  G06F13/16

CPC classification number: G06F3/002 ,  G06F13/1694 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/109 ,  G11C7/222 ,  G11C11/4063 ,  G11C11/4076 ,  G11C2207/2272

Abstract: The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

公开(公告)号：US20190096453A1

公开(公告)日：2019-03-28

申请号：US16038269

申请日：2018-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN-SUNG SHIN ,  Ik-Joon Choi ,  So-Young Kim ,  Tae-Kyu Byun ,  Jae-Youn Youn

IPC: G11C7/10 ,  G06F12/06 ,  G11C7/22 ,  G11C7/06 ,  G06F3/06 ,  G06F7/523

CPC classification number: G11C7/1078 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F7/523 ,  G06F12/0646 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/22 ,  G11C2207/2272 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A stacked memory device includes; a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

公开(公告)号：US20190026046A1

公开(公告)日：2019-01-24

申请号：US15893821

申请日：2018-02-12

Applicant: SK hynix Inc.

Inventor： Kwang Su KIM

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G06F13/00 ,  G11C7/1015 ,  G11C16/06 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2272

Abstract: Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.

公开(公告)号：US20180247683A1

公开(公告)日：2018-08-30

申请号：US15445935

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/109 ,  G11C11/4076 ,  G11C2207/2272

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.