公开(公告)号：US08754656B2

公开(公告)日：2014-06-17

申请号：US13410472

申请日：2012-03-02

Applicant: Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

Inventor： Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

IPC: G01R27/28 ,  G11C29/10 ,  G06F11/00 ,  G01R31/3193 ,  G11C29/50 ,  G11C29/02 ,  G01R31/317

CPC classification number: G01R31/31932 ,  G01R31/31727 ,  G11C29/022 ,  G11C29/50012

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract translation: 高速测试电路从测试仪接收测试仪时钟，并对被测电路进行测试。 高速测试电路根据测试仪时钟产生高频时钟，因此能够在两个频率下工作。 高速测试电路根据高频时钟测试被测电路，并根据例如测试仪时钟的低频时钟执行低速运行。

公开(公告)号：US20060146636A1

公开(公告)日：2006-07-06

申请号：US11339624

申请日：2006-01-26

Applicant: Jen-Shou Hsu ,  Tah-Kang Ting ,  Ming-Hung Wang ,  Bor-Doou Rong

Inventor： Jen-Shou Hsu ,  Tah-Kang Ting ,  Ming-Hung Wang ,  Bor-Doou Rong

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

公开(公告)号：US20060119417A1

公开(公告)日：2006-06-08

申请号：US11005171

申请日：2004-12-06

Applicant: Jenshou Hsu ,  Tah-Kang Ting

Inventor： Jenshou Hsu ,  Tah-Kang Ting

IPC: G05F1/10

CPC classification number: H02M3/073

Abstract: A method and apparatus are provided for improving the efficiency in charge pump systems for low power applications. This first embodiment provides a method and apparatus which defines a charge pump output voltage high target which turns off a charge pump enable signal and a charge pump outlet voltage low target which turns on a charge pump enable signal. A second embodiment defines a protection time where the charge pumping continues until a predefined phase is completed and the leakage paths are disabled. A third embodiment defines a phase memory block, which continues or remembers the phase until the next request for charge pumping. This prevents the circuitry from entering a window where charge leakage, which diminishes charge pumping efficiency, could occur.

Abstract translation: 提供了一种用于提高低功率应用的电荷泵系统的效率的方法和装置。 该第一实施例提供了一种定义电荷泵输出电压高目标的方法和装置，其关闭电荷泵使能信号和导通电荷泵使能信号的电荷泵出口电压低目标。 第二个实施例定义了电荷泵送持续直到预定义相位完成并且泄漏路径被禁用的保护时间。 第三实施例定义了相位存储块，其继续或记住相位，直到下一次对电荷泵送的请求。 这样可防止电路进入可能发生电荷泄漏的电池泄漏，从而降低电荷泵送效率。

公开(公告)号：US20120229146A1

公开(公告)日：2012-09-13

申请号：US13410472

申请日：2012-03-02

Applicant: Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

Inventor： Tah-Kang Ting ,  Gyh-Bin Wang ,  Ming-Hung Wang ,  Chun-Peng Wu ,  Li-Chin Tien

IPC: G01R27/28

CPC classification number: G01R31/31932 ,  G01R31/31727 ,  G11C29/022 ,  G11C29/50012

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract translation: 高速测试电路从测试仪接收测试仪时钟，并对被测电路进行测试。 高速测试电路根据测试仪时钟产生高频时钟，因此能够在两个频率下工作。 高速测试电路根据高频时钟测试被测电路，并根据例如测试仪时钟的低频时钟执行低速运行。

公开(公告)号：US20050270880A1

公开(公告)日：2005-12-08

申请号：US10861157

申请日：2004-06-04

Applicant: Jen-Shoe Hsu ,  Tah-Kang Ting ,  Ming-Hung Wang ,  Bor-Doou Rong

Inventor： Jen-Shoe Hsu ,  Tah-Kang Ting ,  Ming-Hung Wang ,  Bor-Doou Rong

IPC: G11C5/14 ,  G11C7/00 ,  G11C11/4074

CPC classification number: G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract translation: 描述了一种用于存储芯片的深度掉电模式的方法，其中电压调节器和电荷泵关闭，存储单元电压浮起，并且支持电路内部电源电压由从外部芯片电压导出的电压代替 。 在进入深度掉电模式之前，所有存储单元都被置于预充电状态，当进入深度掉电模式时，存储单元电压从该充电状态浮起。 通过电路将外部导出的电压连接到由深度掉电信号控制的支持电路电源电压线。 当存储芯片脱离深度掉电模式时，保持支持电路上的电压偏压可防止闩锁问题。