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    Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
    2.
    发明授权
    Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application 有权
    半导体集成电路采用全速数据转换方案，用于DDR SDRAM内部双倍时钟测试应用

    公开(公告)号：US07404116B2

    公开(公告)日：2008-07-22

    申请号：US10293576

    申请日：2002-11-13

    申请人： Ming-Hung Wang

    发明人： Ming-Hung Wang

    IPC分类号： G11C29/00

    CPC分类号： G11C29/12015 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/401 ,  G11C29/14 ,  G11C2207/107

    摘要： The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.

    摘要翻译： 本发明提供一种用于半导体存储器芯片的全速测试的电路和方法。 本发明提供了一种用于双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）的全速数据转换方案。 对于DDR SDRAM的高速或双速压力测试，内部时钟是外部时钟速度的两倍。 在高速测试期间，这会使数据被写入或呈现给数据通道两次。 本发明提供了一种用于创建全速数据转换方案以克服这种双速测试问题的电路和方法。

    Comparator circuit with Schmitt trigger hysteresis character
    3.
    发明授权
    Comparator circuit with Schmitt trigger hysteresis character 有权
    比较器电路采用施密特触发滞后特性

    公开(公告)号：US07292083B1

    公开(公告)日：2007-11-06

    申请号：US11406464

    申请日：2006-04-18

    申请人： Ming Hung Wang ,  Yen-An Chang

    发明人： Ming Hung Wang ,  Yen-An Chang

    IPC分类号： H03K3/12

    CPC分类号： H03K5/2472

    摘要： A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

    摘要翻译： 提供电路和方法以产生具有施密特触发滞后特性的新型比较器。 该电路包括电流源，其控制通过该比较器电路的电流的大小。 它具有通过参考电压接通的第一逻辑器件，并且第二逻辑器件由比较器输入电压导通。 第一反馈装置由负比较器输出导通。 第一并联电阻器与第一反馈装置并联连接。 第二个反馈装置由正比较器输出导通。 第二并联电阻器与第二反馈装置并联连接。 第一和第二并联电阻用于为差分比较器提供开关电压偏移，这导致施密特触发迟滞特性。

    Fastener assembly for preventing corotation during tightening
    4.
    发明授权
    Fastener assembly for preventing corotation during tightening 失效
    紧固件组件，用于防止紧固过程中的同化

    公开(公告)号：US06343904B1

    公开(公告)日：2002-02-05

    申请号：US09713180

    申请日：2000-11-15

    申请人： Ming-Hung Wang

    发明人： Ming-Hung Wang

    IPC分类号： F16B3300

    CPC分类号： F16B33/00 ,  F16B31/021 ,  F16B35/045 ,  F16B39/24

    摘要： A bolt assembly includes a bolt member, a washer, and a nut. The bolt member includes a head and a shank. The shank has a connecting section that is connected to an article confronting side of the head, an externally threaded section that extends from the connecting section, a breakable tip that extends from the externally threaded section and that is formed with a plurality of axially extending and angularly displaced teeth, and an annular groove that is formed at a juncture of the externally threaded section and the breakable tip. The washer is sleeved on the shank of the bolt member, and has an article confronting side formed with a plurality of spaced apart and radially extending anti-skid projections, and a nut confronting side opposite to the article confronting side of the washer. The nut engages threadedly the externally threaded section of the shank, and has opposing first and second surfaces respectively disposed remote from and proximate to the nut confronting side of the washer such that the second surface of the nut urges the nut confronting side of the washer toward the head of the bolt member.

    摘要翻译： 螺栓组件包括螺栓构件，垫圈和螺母。 螺栓构件包括头部和柄部。 柄部具有与头部相对的物品连接的连接部分，从连接部分延伸的外螺纹部分，从外螺纹部分延伸的可破裂尖端，并且形成有多个轴向延伸和 角度移位的齿，以及形成在外螺纹部分和可破裂尖端的接合处的环形槽。 垫圈套在螺栓构件的柄部上，并且具有形成有多个间隔开并且径向延伸的防滑突起的制品对置面以及与该垫圈相对的物品相对的螺母面对侧。 螺母螺纹地接合柄的外螺纹部分，并且具有相对的第一和第二表面，分别设置在离开垫圈的面对面的螺母的旁边并靠近螺母面对的侧面，使得螺母的第二表面朝向垫圈的面向螺母的侧面 螺栓构件的头部。

    Method and device for adjusting eye range by means of displacements of prisms and ocular lenses
    5.
    发明授权
    Method and device for adjusting eye range by means of displacements of prisms and ocular lenses 失效
    用于通过棱镜和眼镜片的位移来调节眼睛范围的方法和装置

    公开(公告)号：US06236504B1

    公开(公告)日：2001-05-22

    申请号：US09482576

    申请日：2000-01-13

    申请人： Po-Sung Kao ,  Hao Tu ,  Ming-Hung Wang ,  Yuan-Kai Liu

    发明人： Po-Sung Kao ,  Hao Tu ,  Ming-Hung Wang ,  Yuan-Kai Liu

    IPC分类号： G02B2300

    CPC分类号： G02B23/18

    摘要： A method is designed to adjust the distance between the central axes of two ocular lenses of an optical instrument. The method involves the use of a link mechanism to actuate two movable prisms and the two ocular lenses of the optical instrument to move respectively along a base surface such that the optical axes of effective diameters of the two movable prisms are coaxial with the optical axes of the corresponding ocular lenses.

    摘要翻译： 设计一种方法来调节光学仪器的两个眼镜的中心轴之间的距离。 该方法包括使用连杆机构来致动两个可移动棱镜，并且光学仪器的两个目镜透镜分别沿着基面移动，使得两个可移动棱镜的有效直径的光轴与 相应的眼镜。

    Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application
    7.
    发明授权
    Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application 有权
    半导体集成电路采用全速数据转换方案，用于DDR SDRAM内部双倍时钟测试应用

    公开(公告)号：US07676708B2

    公开(公告)日：2010-03-09

    申请号：US12220034

    申请日：2008-07-21

    申请人： Ming-Hung Wang

    发明人： Ming-Hung Wang

    IPC分类号： G11C29/00

    CPC分类号： G11C29/12015 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/401 ,  G11C29/14 ,  G11C2207/107

    摘要： The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.

    摘要翻译： 本发明提供一种用于半导体存储器芯片的全速测试的电路和方法。 本发明提供了一种用于双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）的全速数据转换方案。 对于DDR SDRAM的高速或双速压力测试，内部时钟是外部时钟速度的两倍。 在高速测试期间，这会使数据被写入或呈现给数据通道两次。 本发明提供了一种用于创建全速数据转换方案以克服这种双速测试问题的电路和方法。

    Ring oscillator with a two-stage phase blender for generating multi-phase clock signals
    8.
    发明授权
    Ring oscillator with a two-stage phase blender for generating multi-phase clock signals 有权
    环形振荡器具有两级相位混合器，用于产生多相时钟信号

    公开(公告)号：US07482884B2

    公开(公告)日：2009-01-27

    申请号：US11669944

    申请日：2007-01-31

    申请人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

    发明人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

    IPC分类号： H03B5/24 ,  H03B27/00 ,  H03K3/03

    CPC分类号： H03B27/00 ,  H03K5/13 ,  H03K2005/00052

    摘要： An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

    摘要翻译： 提供了一种用于产生具有环形振荡器的多相时钟信号的装置，包括第一级相位 - 混合器模块和第二级相位 - 混合器模块。 第一级相位 - 搅拌器模块还包括多个差动OP相 - 搅拌器回路。 每个差分式混合器电路都有两个信号输入端，一个输出信号的相位是两个输入信号的插值。 第二级相位混合器模块包括多个逆变器相位混合器电路。 每个逆变器相位混合器电路接收来自第一级相位 - 混合器模块的两个输出信号作为输入，并且输出具有第一级相位 - 混合器模块的两个输出信号的内插相位的时钟信号。

    Self-feedback control pipeline architecture for memory read path applications
    10.
    发明申请
    Self-feedback control pipeline architecture for memory read path applications 有权
    用于存储器读路径应用的自反馈控制流水线架构

    公开(公告)号：US20080031064A1

    公开(公告)日：2008-02-07

    申请号：US11492600

    申请日：2006-07-25

    申请人： Ming Hung Wang ,  Jeng-Tzong Shih

    发明人： Ming Hung Wang ,  Jeng-Tzong Shih

    IPC分类号： G11C7/02

    CPC分类号： G11C7/1039 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/2227 ,  G11C2207/2272 ,  G11C2207/2281

    摘要： A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

    摘要翻译： 存储器读取装置从独立于外部时钟速率的存储器阵列传送数字数据，其中数据传输时间不受外部时钟周期的限制，并且控制的内部时序允许灵活的列选择，并且不会在第 外部时钟信号和内部位线检测就绪信号。 存储器读取装置具有数据读取路径电路和存储器读取控制装置。 数据读取路径电路与存储器进行通信，以获取从存储器读取的所选数据，同步所选择的数据，并从存储器传送所选择的数据。 存储器读取控制装置与用于从存储器中选择要读取的数据的数据读取路径电路通信，用于提供用于同步所选择的数据以从存储器传送的自反馈信号。