摘要:
A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.
摘要:
The invention provides a semiconductor device having a lower probability of erroneous inversion of data signal. The MRAM disclosed herein comprises (m+1)×(n+1) memory cells arranged in (m+1) rows and (n+1) columns, digit lines respectively provided in the rows, and bit lines respectively provided in the columns. A magnetizing current Im caused to flow through a digit line in a selected row makes all memory cells half-selected in the row, while a writing current is caused to flow through (n+1) bit lines to write data signals of (n+1) bits into the (n+1) memory cells, the direction of the writing current depending on the logic of each of these data signals. Thus, erroneous inversion of data signal due to a magnetic field in a digit line is avoided.
摘要:
Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.
摘要:
Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.
摘要:
A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.
摘要:
A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.
摘要:
Each memory cell row is associated with access transistors having their source regions electrically connected together by an n+ diffusion node extending in the direction of the row. The n+ diffusion node is connected to a main word line set to have the low level (a ground voltage) in selecting a corresponding memory cell row. When the main word line is set low, responsively in a data read operation a selected row's word line is set high and in a data write operation a selected row's digit line is set high.
摘要:
During data write, a first driver electrically connects a fist shared node to one of first and second voltages in accordance with write data. A second driver electrically connects a second shared node to the other voltage. A plurality of first switch circuits for electrically connecting one end sides of bit lines to the first shared node, respectively, and a plurality of second switch circuits for electrically connecting the other end sides to the second shared node, respectively, are provided. In accordance with a column select result, the first and second switch circuit for the corresponding bit line are turned on. Therefore, it is possible to execute a data write operation without providing a driver for each bit line.
摘要:
The semiconductor memory device includes a memory cell array, a normal data line pair, a redundant data line pair and a data line switch circuit. The data line switch circuit includes an IO shift decoder decoding the column address and the position information related to a defective data line, and an IO select unit shifting the connection between a data input/output pin and a data line while replacing the defective data line according to the decoded result. High speed data transfer is realized by carrying out simultaneously data line selection and redundancy selection according to the column address.
摘要:
In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.