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公开(公告)号：US20190214070A1
公开(公告)日：2019-07-11
申请号：US16358414
申请日：2019-03-19
CPC分类号： G11C11/1673 , G11C11/16 , G11C11/1675 , G11C17/16 , G11C29/021 , G11C29/023 , G11C29/026 , G11C29/028 , G11C29/12 , G11C29/50
摘要： Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
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公开(公告)号：US20190198752A1
公开(公告)日：2019-06-27
申请号：US16287974
申请日：2019-02-27
发明人： Zihui Wang , Yiming Huai
IPC分类号： H01L43/08 , H01L29/66 , H01F10/32 , H01F41/30 , H01L27/22 , G11C11/15 , H01L43/10 , H01L43/02 , G11C11/16
CPC分类号： H01L43/08 , B82Y40/00 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/3286 , H01F10/329 , H01F41/302 , H01L27/228 , H01L29/66984 , H01L43/02 , H01L43/10
摘要： The present invention is directed to a magnetic memory element including a magnetic free layer structure including one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a magnesium perpendicular enhancement layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the anti-ferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer structure has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.
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公开(公告)号：US20190058110A1
公开(公告)日：2019-02-21
申请号：US15978042
申请日：2018-05-11
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , G11C11/5607 , G11C19/02 , H01F1/009 , H01F10/142 , H01F10/26 , H01F41/20 , H01F41/34 , H01L27/224 , H01L43/10 , H01L43/12
摘要： A magnetic artificial honeycomb lattice comprising a multiplicity of connecting elements separated by hexagonal cylindrical pores, wherein: (a) the hexagonal cylindrical pores: (i) have widths that are substantially uniform and an average width that is in a range of about 15 nm to about 20 nm; and (ii) are substantially equispaced and have an average center-to-center distance that is in a range of about 25 nm to about 35 nm; and (b) the connecting elements comprise a magnetic material layer, and the connecting elements have: (i) lengths that are substantially uniform and an average length that is in a range of about 10 nm to about 15 nm; (ii) widths that are substantially uniform and an average width that is in a range of about 4 nm to about 8 nm; and (iii) a thickness of the magnetic material layer that is substantially uniform and an average thickness that is in a range of about 2 nm to about 8 nm; and (c) the magnetic artificial honeycomb lattice has a surface area, disregarding the presence of the hexagonal cylindrical pores, that is in a range in a range of about 100 mm2 to about 900 mm2.
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公开(公告)号：US20190051340A1
公开(公告)日：2019-02-14
申请号：US16164606
申请日：2018-10-18
发明人： Jun Liu , Gurtej Sandhu
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1695 , H01L43/02
摘要： Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.
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5.发明申请公开(公告)号：US20190035462A1
公开(公告)日：2019-01-31
申请号：US16148100
申请日：2018-10-01
发明人： David H. Wells , Jun Liu
CPC分类号： G11C13/0069 , G11C5/02 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2013/0054
摘要： Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided.
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公开(公告)号：US20180294024A1
公开(公告)日：2018-10-11
申请号：US16005595
申请日：2018-06-11
发明人： Sebastian Schafer , Dmytro Apalkov , Alexey Vasilyevitch Khvalkovskiy , Vladimir Nikitin , Robert Beach , Zheng Duan
CPC分类号： G11C11/161 , G01K7/36 , G01R33/098 , G01R33/14 , G11C7/04 , G11C11/16 , G11C11/1695 , G11C29/50 , G11C2029/5002
摘要： A method for measuring a temperature of magnetic junction switchable using spin transfer. The magnetic junction includes at least one magnetic layer. The method includes measuring a temperature variation of at least one magnetic characteristic for the magnetic layer(s) versus temperature. The method also includes measuring a bias variation in the magnetic characteristic versus an electrical bias for the magnetic junction. This measurement is performed such that spin transfer torque-induced variation(s) in the magnetic characteristic(s) are accounted for. The temperature versus the electrical bias for the magnetic junction is determined based on the temperature variation and the bias variation.
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公开(公告)号：US10079338B2
公开(公告)日：2018-09-18
申请号：US15794983
申请日：2017-10-26
发明人： Yiming Huai , Huadong Gan , Bing K. Yen
IPC分类号： H01L43/08 , H01F10/32 , G11C11/16 , H01L29/66 , H01L43/10 , H01L27/22 , H01F41/30 , H01L43/02 , B82Y40/00
CPC分类号： H01L43/08 , B82Y40/00 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/3286 , H01F10/329 , H01F41/302 , H01L27/228 , H01L29/66984 , H01L43/02 , H01L43/10
摘要： The present invention is directed to a magnetic memory element including a magnetic free layer structure having a variable magnetization direction perpendicular to a layer plane thereof; an oxide layer formed adjacent to the magnetic free layer structure; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure opposite the oxide layer; a first magnetic reference layer formed adjacent to the insulating tunnel junction layer opposite the magnetic free layer structure; a second magnetic reference layer separated from the first magnetic reference layer by a perpendicular enhancement layer; an antiferromagnetic coupling layer formed adjacent to the second magnetic reference layer; and a magnetic fixed layer structure formed adjacent to the antiferromagnetic coupling layer. The first and second magnetic reference layers have a first invariable magnetization direction substantially perpendicular to layer planes thereof. The magnetic fixed layer structure has a second invariable magnetization direction substantially opposite to the first invariable magnetization direction.
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公开(公告)号：US10055232B2
公开(公告)日：2018-08-21
申请号：US14612367
申请日：2015-02-03
发明人： Yoshiyuki Kurokawa
IPC分类号： G06F9/00 , G06F15/177 , G06F9/4401 , G11C11/16 , G11C7/20 , G11C8/16 , G11C14/00 , G11C16/08 , H01L43/08 , H01L27/22
CPC分类号： G06F9/4401 , G11C7/20 , G11C8/16 , G11C11/16 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1693 , G11C11/1697 , G11C14/0081 , G11C16/08 , G11C2213/74 , G11C2213/79 , H01L27/228 , H01L43/08
摘要： A semiconductor device in which the area of a circuit that is not in use during normal operation can be reduced is provided. A semiconductor device including a memory circuit has a function of storing a start-up routine in the memory circuit and executing the start-up routine; a function of operating the memory circuit as a buffer memory device after executing the start-up routine; and a function of loading the start-up routine into the memory circuit from the outside before the semiconductor device is powered off. The memory circuit has a plurality of groups each including at least a first transistor, a second transistor, and a memory element including an MTJ element. The memory element has a function of storing a signal input through the first transistor. The second transistor has a function of being turned on or off in accordance with the signal stored in the memory elements.
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公开(公告)号：US20180226571A1
公开(公告)日：2018-08-09
申请号：US15947053
申请日：2018-04-06
申请人： SONY CORPORATION
CPC分类号： H01L43/08 , G11C11/16 , H01L27/1203 , H01L27/228 , H01L43/02 , H01L43/12
摘要： The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat.A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
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公开(公告)号：US20180205005A1
公开(公告)日：2018-07-19
申请号：US15923842
申请日：2018-03-16
发明人： Wenchin LIN , Jason JANESKY
IPC分类号： H01L43/02 , H01L23/552 , G11C5/00 , H01L23/14 , H01L27/22 , H01L43/12 , H01L23/00 , H01L23/498 , H01L23/13 , G11C11/16
CPC分类号： H01L43/02 , G11C5/005 , G11C11/16 , H01L23/13 , H01L23/14 , H01L23/49816 , H01L23/49838 , H01L23/552 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L27/222 , H01L43/12 , H01L2224/04042 , H01L2224/06136 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45015 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/83191 , H01L2224/83192 , H01L2224/85203 , H01L2224/85205 , H01L2224/92147 , H01L2924/00014 , H01L2924/1441 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2924/207
摘要： Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.
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