公开(公告)号：US20070029677A1

公开(公告)日：2007-02-08

申请号：US11488634

申请日：2006-07-19

申请人： Takao Kamoshima ,  Yasuhisa Fujii ,  Takeshi Masamitsu

发明人： Takao Kamoshima ,  Yasuhisa Fujii ,  Takeshi Masamitsu

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnection structure includes a lower interconnection layer formed on a substrate and composed of a copper layer, an interlayer insulating layer formed on the lower interconnection layer and having a via reaching the lower interconnection layer, an upper interconnection layer electrically connected to the lower interconnection layer through the via, and composed of a copper layer formed in the interlayer insulating layer, and a barrier metal layer formed between the upper interconnection layer and the interlayer insulating layer. The barrier metal layer has an opening in a bottom portion of the via, and through that opening, the upper interconnection layer comes in direct contact with the lower interconnection layer in the bottom portion of the via. Thus, an interconnection structure suppressing concentration of voids in an interconnection under a via due to stress migration can be attained.

摘要翻译： 互连结构包括形成在基板上并由铜层构成的下互连层，形成在下布线层上并具有到达下互连层的通孔的层间绝缘层，与互连层下电连接的上互连层 并且由形成在层间绝缘层中的铜层构成，以及形成在上互连层和层间绝缘层之间的阻挡金属层。 阻挡金属层在通孔的底部具有开口，并且通过该开口，上互连层与通孔的底部中的下互连层直接接触。 因此，可以获得抑制由于应力迁移导致的通孔内的互连中的空隙浓度的互连结构。

公开(公告)号：US06696732B2

公开(公告)日：2004-02-24

申请号：US10192610

申请日：2002-07-11

申请人： Takeru Matsuoka ,  Shoichi Fukui ,  Takeshi Masamitsu

发明人： Takeru Matsuoka ,  Shoichi Fukui ,  Takeshi Masamitsu

IPC分类号： H01L2994

CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L23/535 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.

摘要翻译： 多个MOS型FET器件14和16设置在半导体衬底12上。在其上提供下层间绝缘膜20。 在下部层间绝缘膜20中限定从多个FET器件的栅极电极14c经由源极/漏极区域14b和16a延伸的每个通孔22.局部布线24被埋入通孔22中 连接每个栅电极14c和源/漏区14b和16a。 此外，在局部布线24和下层间绝缘膜20上设置上层绝缘膜26.上层电极层28设置在上层间绝缘膜26的表面上。