公开(公告)号：US06696732B2

公开(公告)日：2004-02-24

申请号：US10192610

申请日：2002-07-11

申请人： Takeru Matsuoka ,  Shoichi Fukui ,  Takeshi Masamitsu

发明人： Takeru Matsuoka ,  Shoichi Fukui ,  Takeshi Masamitsu

IPC分类号： H01L2994

CPC分类号： H01L21/823475 ,  H01L21/76895 ,  H01L23/535 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.

摘要翻译： 多个MOS型FET器件14和16设置在半导体衬底12上。在其上提供下层间绝缘膜20。 在下部层间绝缘膜20中限定从多个FET器件的栅极电极14c经由源极/漏极区域14b和16a延伸的每个通孔22.局部布线24被埋入通孔22中 连接每个栅电极14c和源/漏区14b和16a。 此外，在局部布线24和下层间绝缘膜20上设置上层绝缘膜26.上层电极层28设置在上层间绝缘膜26的表面上。

公开(公告)号：US06683000B2

公开(公告)日：2004-01-27

申请号：US10228307

申请日：2002-08-27

申请人： Shoichi Fukui ,  Takeru Matsuoka

发明人： Shoichi Fukui ,  Takeru Matsuoka

IPC分类号： H01L2144

CPC分类号： H01L21/76877

摘要： A semiconductor-device fabrication method includes a step of forming a contact hole in a semiconductor substrate 1 and a step of forming a conductive contact hole. The step of forming the contact hole is performed by repeating two times or more a burying step of depositing a conductive material 5 to bury the conductive material in the contact hole and an etch-back step of removing the conductive material around the contact hole by etch back.

摘要翻译： 半导体器件制造方法包括在半导体衬底1中形成接触孔的步骤和形成导电接触孔的步骤。 形成接触孔的步骤通过重复两次或更多次沉积导电材料5以将导电材料埋入接触孔中的掩埋步骤和通过蚀刻去除接触孔周围的导电材料的回蚀步骤来进行 背部。

公开(公告)号：US08008730B2

公开(公告)日：2011-08-30

申请号：US12502008

申请日：2009-07-13

申请人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

发明人： Shoichi Fukui ,  Noboru Morimoto ,  Yasutaka Nishioka ,  Junko Izumitani ,  Atsushi Ishii

IPC分类号： H01L21/02

CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/76849 ,  H01L21/76867 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.

摘要翻译： 提供能提高半导体器件的可靠性的半导体器件的制造方法。 用于覆盖半导体衬底中形成的半导体元件的第一绝缘膜通过具有良好嵌入特性的热CVD法等形成。 通过等离子体CVD法形成第二绝缘膜以覆盖第一绝缘膜，其具有优异的耐湿性。 形成插塞以穿透第一绝缘膜和第二绝缘膜。 在第二绝缘膜上形成由具有较低介电常数的低k膜构成的第三绝缘膜。 通过镶嵌技术在第三绝缘膜中形成布线以与插头电耦合。

公开(公告)号：US20110001246A1

公开(公告)日：2011-01-06

申请号：US12883031

申请日：2010-09-15

申请人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US20080230847A1

公开(公告)日：2008-09-25

申请号：US12014078

申请日：2008-01-14

申请人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US08203210B2

公开(公告)日：2012-06-19

申请号：US12883031

申请日：2010-09-15

申请人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US20090289367A1

公开(公告)日：2009-11-26

申请号：US12472100

申请日：2009-05-26

申请人： Daisuke KODAMA ,  Shoichi Fukui ,  Hiroshi Miyazaki ,  Tatsunori Murata

发明人： Daisuke KODAMA ,  Shoichi Fukui ,  Hiroshi Miyazaki ,  Tatsunori Murata

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/76832 ,  H01L23/53295 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A copper interconnection layer is formed in an interconnection trench at a surface of an interlayer insulating film. A diffusion preventing insulating film is formed to cover the copper interconnection layer and is made of at least one of SiC and SiCN. An insulating film is formed on the copper interconnection layer with the diffusion preventing insulating film interposed and is made of SiN.

摘要翻译： 在层间绝缘膜的表面的互连沟槽中形成铜互连层。 形成扩散防止绝缘膜以覆盖铜互连层，并且由SiC和SiCN中的至少一种制成。 在铜互连层上形成有绝缘膜，其中扩散防止绝缘膜插入并由SiN制成。

公开(公告)号：US06438243B1

公开(公告)日：2002-08-20

申请号：US09085047

申请日：1998-05-27

申请人： Naoki Ikeuchi ,  Muneo Harada ,  Shoichi Fukui ,  Takahiko Oasa ,  Shigeru Ando ,  Kenji Tanaka

发明人： Naoki Ikeuchi ,  Muneo Harada ,  Shoichi Fukui ,  Takahiko Oasa ,  Shigeru Ando ,  Kenji Tanaka

IPC分类号： H04R2500

CPC分类号： H04R15/02

摘要： A vibration wave detector having a first diaphragm for receiving vibration waves, such as sound waves and so on, to be propagated in a medium, a resonant unit having a plurality of cantilever resonators each having such a length as to resonate at an individual predetermined frequency, a retaining rod for retaining the resonant unit, a second diaphragm positioned on the opposite side of the first diaphragm with respect to the retaining rod, and a vibration intensity detector for detecting the vibration intensity, for each predetermined frequency, of each of the resonators, by the vibration waves received by the first diaphragm and propagated to the resonant unit through the retaining rod.

摘要翻译： 一种振动波检测器，具有用于接收诸如声波等的振动波在介质中传播的第一振动膜，具有多个悬臂谐振器的谐振单元，每个悬臂谐振器具有以各个预定频率谐振的长度 ，用于保持谐振单元的保持杆，相对于保持杆定位在第一隔膜相对侧的第二隔膜，以及用于检测每个谐振器的每个预定频率的振动强度的振动强度检测器 通过由第一隔膜接收的振动波并通过保持杆传播到谐振单元。

公开(公告)号：US20110298070A1

公开(公告)日：2011-12-08

申请号：US13150968

申请日：2011-06-01

申请人： Shoichi Fukui ,  Satoshi Iida ,  Shinroku Maejima ,  Kazuyuki Omori

发明人： Shoichi Fukui ,  Satoshi Iida ,  Shinroku Maejima ,  Kazuyuki Omori

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device has a magnetoresistive element, a bit line over the magnetoresistive element, and a yoke cover over the bit line. To form the yoke cover, a laminate film is first formed over the bit line, the laminate film having a first barrier metal layer, a magnetic layer, and a second barrier metal layer which are formed successively over the bit line. Then, the laminate film is subjected to: reactive ion etching with a gas mixture of a carbon tetrafluoride (CF4) gas and an argon (Ar) gas, reactive ion etching with a gas mixture of carbon monoxide (CO), an ammonia (NH3) gas, and an argon (Ar) gas, and reactive ion etching with a gas mixture of a carbon tetrafluoride (CF4) gas and an argon (Ar) gas.

摘要翻译： 半导体器件具有磁阻元件，磁阻元件上的位线和位线上的磁轭盖。 为了形成轭盖，首先在位线上形成层压膜，层压膜具有在位线上连续形成的第一阻挡金属层，磁性层和第二阻挡金属层。 然后，利用四氟化碳（CF 4）气体和氩气（Ar）气体的气体混合物对层压膜进行反应离子蚀刻，用一氧化碳（CO），氨（NH 3）的气体混合物进行反应离子蚀刻 ）气体和氩（Ar）气体，以及用四氟化碳（CF 4）气体和氩气（Ar）气体的气体混合物的反应离子蚀刻。

公开(公告)号：US20110062539A1

公开(公告)日：2011-03-17

申请号：US12885093

申请日：2010-09-17

申请人： Ryoji MATSUDA ,  Motoi Ashida ,  Shuichi Ueno ,  Shoichi Fukui ,  Shinya Hirano ,  Seiji Muranaka ,  Kazuyuki Omori

发明人： Ryoji MATSUDA ,  Motoi Ashida ,  Shuichi Ueno ,  Shoichi Fukui ,  Shinya Hirano ,  Seiji Muranaka ,  Kazuyuki Omori

IPC分类号： H01L29/82 ,  H01L21/04

CPC分类号： H01L27/228 ,  B82Y25/00 ,  H01F10/131 ,  H01F10/14 ,  H01F10/142 ,  H01F10/145 ,  H01F10/20 ,  H01F10/22 ,  H01F10/3254 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76844 ,  H01L27/105 ,  H01L43/08 ,  H01L43/12

摘要： To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material.

摘要翻译： 提供抑制重写特性劣化的半导体器件。 在存储单元区域中，半导体磁存储器件中的磁阻元件形成为阵列形状，其方式是将磁阻元件布置在沿一个方向延伸的数字线与沿大致垂直于 数字线。 数字线和位线具有这样一种布线结构，其通过用覆盖层覆盖作为布线主体的铜膜而构成。 磁阻元件的一端侧经由由非磁性材料形成的顶部通孔电耦合到位线。