公开(公告)号：US06194752B1

公开(公告)日：2001-02-27

申请号：US09094592

申请日：1998-06-15

申请人： Satoru Ogasahara ,  Mitsuaki Harada ,  Hiroaki Furukawa ,  Takashi Goto ,  Tatsuro Gueshi ,  Yoshiyuki Ishizuka

发明人： Satoru Ogasahara ,  Mitsuaki Harada ,  Hiroaki Furukawa ,  Takashi Goto ,  Tatsuro Gueshi ,  Yoshiyuki Ishizuka

IPC分类号： H01L2972

CPC分类号： H01L28/55 ,  H01L29/78391

摘要： A gate insulating layer and a first lower electrode are formed on a channel region of a silicon substrate, and an interlayer insulating film is formed on the silicon substrate so as to cover the first lower electrode and the gate insulating film. A buffer layer is formed on the interlayer insulating film, and a contact hole is formed in the interlayer insulating film and the buffer layer on the first lower electrode. A connecting layer and a second lower electrode are formed in the contact hole. A ferroelectric thin film and an upper electrode are formed in this order on the buffer layer so as to be brought into contact with the upper surface of the second lower electrode.

摘要翻译： 在硅衬底的沟道区上形成栅绝缘层和第一下电极，在硅衬底上形成层间绝缘膜，以覆盖第一下电极和栅极绝缘膜。 在层间绝缘膜上形成缓冲层，在层间绝缘膜和第一下电极的缓冲层上形成接触孔。 连接层和第二下电极形成在接触孔中。 在缓冲层上依次形成铁电薄膜和上电极，以与第二下电极的上表面接触。