公开(公告)号：US20090204658A1

公开(公告)日：2009-08-13

申请号：US12428288

申请日：2009-04-22

申请人： Hisashi ITO ,  Tetsuichi NAKAE

发明人： Hisashi ITO ,  Tetsuichi NAKAE

IPC分类号： G06F7/32

CPC分类号： G06F7/492 ,  G06F5/16 ,  G06F9/30014 ,  G06F2207/3816 ,  G06F2207/4911

摘要： A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a calculation-instruction memory section which stores the calculation instruction having the number of calculation digits and a type of calculation set therein, and a decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in the plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in the calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in the calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in the plurality of memory areas of the multidigit memory section digit unit by digit unit.

摘要翻译： 在计算指令中设置的计算数字的数量进行多位数十进制计算的十进制计算装置包括：多位存储部，其存储比多个存储器中的规定数字部的位数大的位数 区域，存储具有计算数字数量的计算指令和其中设置的计算类型的计算指令存储部分，以及执行十进制计算部分，其执行依次计算分别存储在多个数据中的对应数字单元的数值 存储在计算指令存储器部分中的计算指令中设置的计算位数的数字单元，按计算指令存储部分存储的计算指令中设置的计算类型进行十进制计算， 指令记忆部分 并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域中。

公开(公告)号：US5157215A

公开(公告)日：1992-10-20

申请号：US583966

申请日：1990-09-14

申请人： Tetsuichi Nakae ,  Takashi Matsuda

发明人： Tetsuichi Nakae ,  Takashi Matsuda

IPC分类号： G10H1/00 ,  G10H1/12 ,  G10H5/00 ,  G10L11/02

CPC分类号： G10H1/125 ,  G10H5/002 ,  G10H5/005 ,  G10L25/78 ,  G10H2250/475 ,  Y10S84/09 ,  Y10S84/11

摘要： An electrical musical instrument includes a scale designator for sequentially and automatically designating a scale on the basis of prestored data of a music piece, and a musical tone signal generator for outputting a musical tone signal including a harmonic frequency on the basis of the scale designated by said scale designator or as a fundamental frequency. A voice detector detects an external voice and the detected voice is divided by a modulator into voice signals in a plurality of frequency ranges. The musical tone signal is modulated in units of corresponding frequency ranges on the basis of the voice signals divided into the plurality of frequency ranges.

摘要翻译： 一种电气乐器，包括：一个比例指示器，用于根据音乐片段的预先存储的数据顺序和自动地指定刻度;以及乐音信号发生器，用于根据由音乐片段指定的刻度输出包括谐波频率的音调信号 规模指示器或基本频率。 语音检测器检测外部语音，并且将检测到的语音由调制器分割成多个频率范围内的语音信号。 基于分成多个频率范围的语音信号，以对应的频率范围为单位调制乐音信号。

公开(公告)号：US20090133566A1

公开(公告)日：2009-05-28

申请号：US12255777

申请日：2008-10-22

申请人： Tetsuichi NAKAE

发明人： Tetsuichi NAKAE

IPC分类号： G10H7/00

CPC分类号： G10H1/0091 ,  G10H2210/281 ,  G10H2250/115 ,  G10H2250/621 ,  H04S7/305

摘要： A reverberation effect adding device comprising a first convolution circuit which in turn comprises FIR filters (80-1 to 80-4) and an adder (accumulator) (81) which adds outputs from the FIR filters, a moving average circuit (82) which receives musical sound waveform data delayed by a predetermined number of stages in the first convolution circuit and which outputs averaged second musical sound waveform data obtained by sampling at a second sampling frequency lower than the first sampling frequency, a second convolution circuit which in turn comprises FIR filters (80-5 to 80-28) which sequentially receive the second musical sound waveform data obtained by sampling at the second sampling frequency and an adder (accumulator) (83), an interpolator (84) which receives an output from the adder (83) of the second convolution circuit, calculates an interpolated value of the output value from the adder (83), and provides the output from the adder (83) and the interpolated value from the interpolator (84) sequentially at the first sampling frequency, and an adder (85) which adds the outputs from the adder (81) and the interpolator (84) and outputs a result of the addition as reverberation data.

摘要翻译： 一种混响效果添加装置，包括第一卷积电路，该第一卷积电路又包括FIR滤波器（80-1至80-4）和加法器（累加器）（81），其加上来自FIR滤波器的输出;移动平均电路（82） 接收在第一卷积电路中延迟预定级数的音乐声波形数据，并输出通过以低于第一采样频率的第二采样频率进行采样获得的平均的第二音乐声波形数据;第二卷积电路，其又包括FIR 滤波器（80-5至80-28），其顺序地接收通过以第二采样频率采样获得的第二音乐波形数据和加法器（累加器）（83），接收来自加法器的输出的内插器（84） 83），从加法器（83）计算输出值的内插值，并从加法器（83）提供输出，并从插值中提供内插值 （84），以及将来自加法器（81）和内插器（84）的输出相加的加法器（85），并将该相加结果作为混响数据输出。

公开(公告)号：US07947891B2

公开(公告)日：2011-05-24

申请号：US12418789

申请日：2009-04-06

申请人： Tetsuichi Nakae

发明人： Tetsuichi Nakae

IPC分类号： G10H1/00

CPC分类号： G10H1/125 ,  G10H7/12 ,  G10H2250/615

摘要： A product-sum operation circuit has delay circuits of the first to the (n−1)th stage for delaying musical tone data, multiplying circuits 60-6(n−1) for multiplying the musical signal data or the delayed musical signal data output from the delay circuits by impulse response coefficients, and adders 71-7(n−1) for summing up data output from the multiplying circuits. The product-sum operation circuit is provided with a feed back circuit. The feed back circuit includes a multiplying circuit 80 that receives the delayed data from the delay circuit at the (n−1)th stage and multiplies the received data by a multiplication coefficient, and an adder 81 for adding data from the multiplying circuit 80 to the delayed data from the delay circuit at the “p”th stage.

摘要翻译： 乘积和运算电路具有用于延迟乐音数据的第一至第（n-1）级的延迟电路，用于乘以音乐信号数据或延迟音乐数据输出的乘法电路60-6（n-1） 通过脉冲响应系数从延迟电路和用于对乘法电路输出的数据求和的加法器71-7（n-1）。 产品总和运算电路设有反馈电路。 反馈电路包括乘法电路80，其在第（n-1）级从延迟电路接收延迟的数据，并将接收的数据乘以乘法系数;以及加法器81，用于将来自乘法电路80的数据加到 来自延迟电路在“p”阶段的延迟数据。

公开(公告)号：US20090266219A1

公开(公告)日：2009-10-29

申请号：US12418789

申请日：2009-04-06

申请人： Tetsuichi NAKAE

发明人： Tetsuichi NAKAE

IPC分类号： G10C3/26

CPC分类号： G10H1/125 ,  G10H7/12 ,  G10H2250/615

摘要： A product-sum operation circuit has delay circuits of the first to the (n−1)th stage for delaying musical tone data, multiplying circuits 60-6(n−1) for multiplying the musical signal data or the delayed musical signal data output from the delay circuits by impulse response coefficients, and adders 71-7(n−1) for summing up data output from the multiplying circuits. The product-sum operation circuit is provided with a feed back circuit. The feed back circuit includes a multiplying circuit 80 that receives the delayed data from the delay circuit at the (n-1)th stage and multiplies the received data by a multiplication coefficient, and an adder 81 for adding data from the multiplying circuit 80 to the delayed data from the delay circuit at the “p”th stage.

摘要翻译： 乘积和运算电路具有用于延迟乐音数据的第一至第（n-1）级的延迟电路，用于乘以音乐信号数据或延迟音乐数据输出的乘法电路60-6（n-1） 通过脉冲响应系数从延迟电路和用于对乘法电路输出的数据求和的加法器71-7（n-1）。 产品总和运算电路设有反馈电路。 反馈电路包括乘法电路80，其在第（n-1）级从延迟电路接收延迟的数据，并将接收的数据乘以乘法系数;以及加法器81，用于将来自乘法电路80的数据加到 来自延迟电路在“p”阶段的延迟数据。

公开(公告)号：US08316067B2

公开(公告)日：2012-11-20

申请号：US12428288

申请日：2009-04-22

申请人： Hisashi Ito ,  Tetsuichi Nakae

发明人： Hisashi Ito ,  Tetsuichi Nakae

IPC分类号： G06F3/00 ,  G06F7/38

CPC分类号： G06F7/492 ,  G06F5/16 ,  G06F9/30014 ,  G06F2207/3816 ,  G06F2207/4911

摘要： A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a calculation-instruction memory section which stores the calculation instruction having the number of calculation digits and a type of calculation set therein, and a decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in the plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in the calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in the calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in the plurality of memory areas of the multidigit memory section digit unit by digit unit.

摘要翻译： 在计算指令中设置的计算数字的数量进行多位数十进制计算的十进制计算装置包括：多位存储部，其存储比多个存储器中的规定数字部的位数大的位数 区域，存储具有计算数字数量的计算指令和其中设置的计算类型的计算指令存储部分，以及执行十进制计算部分，其执行依次计算分别存储在多个数据中的对应数字单元的数值 存储在计算指令存储器部分中的计算指令中设置的计算位数的数字单元，按计算指令存储部分存储的计算指令中设置的计算类型进行十进制计算， 指令记忆部分 并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域中。

公开(公告)号：US07716267B2

公开(公告)日：2010-05-11

申请号：US11109888

申请日：2005-04-19

申请人： Hisashi Ito ,  Tetsuichi Nakae

发明人： Hisashi Ito ,  Tetsuichi Nakae

IPC分类号： G06F7/38 ,  G06F7/50

CPC分类号： G06F7/492 ,  G06F5/16 ,  G06F9/30014 ,  G06F2207/3816 ,  G06F2207/4911

摘要： Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits of a predetermined digit unit in plurality of memory areas; calculation-instruction memory section which stores calculation instruction having the number of calculation digits and type of calculation set therein; and decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in plurality of memory areas of multidigit memory section digit unit by digit unit.

摘要翻译： 十进制计算装置，其在计算指令中设置的计算数字的数量进行多位数十进制计算，包括多位存储器部分，其能够存储具有比多个存储区域中的预定数字单元的位数更大的位数的值; 计算指令存储部，其存储具有计算数的个数和其中设定的计算类型的计算指令; 和十进制计算部分，执行十进制计算，其执行十进制计算，其顺次计算分别存储在多位存储部分的多个存储区域中的数字单位的数值，以计数指令中存储的计算指令中设置的计算数字的数量为单位的数字单位 存储器部分，根据存储在计算指令存储器部分中的计算指令中设置的计算类型进行十进制计算，并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域。

公开(公告)号：US07612281B2

公开(公告)日：2009-11-03

申请号：US12255777

申请日：2008-10-22

申请人： Tetsuichi Nakae

发明人： Tetsuichi Nakae

IPC分类号： G10H7/10

CPC分类号： G10H1/0091 ,  G10H2210/281 ,  G10H2250/115 ,  G10H2250/621 ,  H04S7/305

摘要： A reverberation effect adding device comprising a first convolution circuit which in turn comprises FIR filters (80-1 to 80-4) and an adder (accumulator) (81) which adds outputs from the FIR filters, a moving average circuit (82) which receives musical sound waveform data delayed by a predetermined number of stages in the first convolution circuit and which outputs averaged second musical sound waveform data obtained by sampling at a second sampling frequency lower than the first sampling frequency, a second convolution circuit which in turn comprises FIR filters (80-5 to 80-28) which sequentially receive the second musical sound waveform data obtained by sampling at the second sampling frequency and an adder (accumulator) (83), an interpolator (84) which receives an output from the adder (83) of the second convolution circuit, calculates an interpolated value of the output value from the adder (83), and provides the output from the adder (83) and the interpolated value from the interpolator (84) sequentially at the first sampling frequency, and an adder (85) which adds the outputs from the adder (81) and the interpolator (84) and outputs a result of the addition as reverberation data.

摘要翻译： 一种混响效果添加装置，包括第一卷积电路，该第一卷积电路又包括FIR滤波器（80-1至80-4）和加法器（累加器）（81），其加上来自FIR滤波器的输出;移动平均电路（82） 接收在第一卷积电路中延迟预定级数的音乐声波形数据，并输出通过以低于第一采样频率的第二采样频率进行采样获得的平均的第二音乐声波形数据;第二卷积电路，其又包括FIR 滤波器（80-5至80-28），其顺序地接收通过以第二采样频率采样获得的第二音乐波形数据和加法器（累加器）（83），接收来自加法器的输出的内插器（84） 83），从加法器（83）计算输出值的内插值，并从加法器（83）提供输出，并从插值中提供内插值 （84），以及将来自加法器（81）和内插器（84）的输出相加的加法器（85），并将该相加结果作为混响数据输出。

公开(公告)号：US20060047740A1

公开(公告)日：2006-03-02

申请号：US11109888

申请日：2005-04-19

申请人： Hisashi Ito ,  Tetsuichi Nakae

发明人： Hisashi Ito ,  Tetsuichi Nakae

IPC分类号： G06F7/52

CPC分类号： G06F7/492 ,  G06F5/16 ,  G06F9/30014 ,  G06F2207/3816 ,  G06F2207/4911

摘要： Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits of a predetermined digit unit in plurality of memory areas; calculation-instruction memory section which stores calculation instruction having the number of calculation digits and type of calculation set therein; and decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in plurality of memory areas of multidigit memory section digit unit by digit unit.

摘要翻译： 十进制计算装置，其在计算指令中设置的计算数字的数量进行多位数十进制计算，包括多位存储器部分，其能够存储具有比多个存储区域中的预定数字单元的位数更大的位数的值; 计算指令存储部，其存储具有计算数的个数和其中设定的计算类型的计算指令; 和十进制计算部分，执行十进制计算，其执行十进制计算，其顺次计算分别存储在多位存储部分的多个存储区域中的数字单位的数值，以计数指令中存储的计算指令中设置的计算数字的数量为单位的数字单位 存储器部分，根据存储在计算指令存储器部分中的计算指令中设置的计算类型进行十进制计算，并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域。

公开(公告)号：US5943049A

公开(公告)日：1999-08-24

申请号：US636774

申请日：1996-04-23

申请人： Kunihiro Matsubara ,  Tetsuichi Nakae ,  Hirohisa Koyama ,  Atsushi Inoshita ,  Kazuhisa Nakamura ,  Koji Toriyama

发明人： Kunihiro Matsubara ,  Tetsuichi Nakae ,  Hirohisa Koyama ,  Atsushi Inoshita ,  Kazuhisa Nakamura ,  Koji Toriyama

IPC分类号： G06T11/00 ,  G06F3/00

CPC分类号： G06T11/00

摘要： A plurality of images each indicative of a file to be processed or its items to be processed is displayed on a display. When message information is displayed which is to be transmitted to the user with respect to each of the images, a surrounding image which surrounds the message information is displayed to emphasize and display the message information. When a face image is displayed on the display screen, the message information is displayed in the form of a balloon used frequently in a cartoon or animation as if the message information were uttered from the face image. The displayed shape of the balloon is changed in accordance with attributes of the face image displayed on the display screen so as to harmonize with the face image.

摘要翻译： 在显示器上显示各自指示要处理的文件或其要处理的项目的多个图像。 当显示要针对每个图像发送给用户的消息信息时，围绕消息信息的周围图像被显示以强调和显示消息信息。 当在显示屏幕上显示面部图像时，消息信息以卡通或动画中频繁使用的气球的形式显示，就像从脸部图像发出消息信息一样。 根据显示在显示屏幕上的面部图像的属性来改变气球的显示形状，以便与脸部图像协调。