公开(公告)号：US09330733B1

公开(公告)日：2016-05-03

申请号：US13012717

申请日：2011-01-24

申请人： Russell George Tessier ,  Vaughn Timothy Betz ,  Thiagaraja Golpalsamy ,  David Neto

发明人： Russell George Tessier ,  Vaughn Timothy Betz ,  Thiagaraja Golpalsamy ,  David Neto

IPC分类号： G06F12/00 ,  G11C5/14

CPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

摘要翻译： 逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。 逻辑存储器可以自动映射到许多潜在的物理实现。 对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。 当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。 读使能和写使能信号可以转换为功能等效的时钟使能信号。 可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。 潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。

公开(公告)号：US07877555B1

公开(公告)日：2011-01-25

申请号：US11510018

申请日：2006-08-24

申请人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

发明人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

IPC分类号： G06F12/00

CPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

摘要翻译： 逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。 逻辑存储器可以自动映射到许多潜在的物理实现。 对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。 当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。 读使能和写使能信号可以转换为功能等效的时钟使能信号。 可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。 潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。