利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.016 秒)

    Power-aware RAM processing
    1.
    发明授权
    Power-aware RAM processing 有权
    电源感知RAM处理

    公开(公告)号：US09330733B1

    公开(公告)日：2016-05-03

    申请号：US13012717

    申请日：2011-01-24

    申请人： Russell George Tessier ,  Vaughn Timothy Betz ,  Thiagaraja Golpalsamy ,  David Neto

    发明人： Russell George Tessier ,  Vaughn Timothy Betz ,  Thiagaraja Golpalsamy ,  David Neto

    IPC分类号： G06F12/00 ,  G11C5/14

    CPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

    摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

    摘要翻译： 逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。 逻辑存储器可以自动映射到许多潜在的物理实现。 对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。 当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。 读使能和写使能信号可以转换为功能等效的时钟使能信号。 可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。 潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。

    Method of optimizing the design of electronic systems having multiple timing constraints
    4.
    发明授权
    Method of optimizing the design of electronic systems having multiple timing constraints 有权
    优化具有多个时序约束的电子系统设计的方法

    公开(公告)号：US06763506B1

    公开(公告)日：2004-07-13

    申请号：US09792296

    申请日：2001-02-23

    申请人： Vaughn Timothy Betz ,  David Reid Galloway

    发明人： Vaughn Timothy Betz ,  David Reid Galloway

    IPC分类号： G06F1750

    CPC分类号： G06F17/5031 ,  G06F17/5045

    摘要： An electronic representation of the electronic design is received which includes various connections between various blocks specifying functions performed within the electronic design. Each of the connections forms part of one or more paths through at least a portion of the electronic design. Each path has an associated timing constraint. The method assigns criticality values to at least one of the connections. These criticality values are based upon a slack ratio that is a function of the timing constraints and values of slack for paths on which the connections reside. The electronic representation may be revised in a manner that biases the representation toward a state in which connections having relatively high criticality are not changed in a manner which increases the delay in those connections or are changed in a manner that reduces delay. In some cases, the timing constraints for a path, and possibly all coupled paths, are relaxed when a connection has a negative slack ratio, negative slack, or routability problems.

    摘要翻译： 接收电子设计的电子表示，其包括指定在电子设计中执行的功能的各种块之间的各种连接。 每个连接形成通过电子设计的至少一部分的一个或多个路径的一部分。 每个路径都有相关的时序约束。 该方法将关键性值分配给至少一个连接。 这些临界值基于作为连接所在路径的时序约束和松弛值的函数的松弛比。 电子表示可以以使得表示偏向具有相对高临界性的连接不以增加那些连接中的延迟或以减少延迟的方式改变的方式改变的方式来修改。 在一些情况下，当连接具有负的松弛比，负的松弛或可解决性问题时，路径的时序约束以及可能的所有耦合的路径被放宽。

    Versatile logic element and logic array block
    7.
    发明授权
    Versatile logic element and logic array block 有权

    公开(公告)号：US07218133B2

    公开(公告)日：2007-05-15

    申请号：US11050111

    申请日：2005-02-02

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Timothy Betz

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Timothy Betz

    IPC分类号： H03K19/003

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Field Programmable Gate-Array with Embedded Network-on-Chip Hardware and Design Flow
    8.
    发明申请
    Field Programmable Gate-Array with Embedded Network-on-Chip Hardware and Design Flow 审中-公开
    具有嵌入式网络芯片硬件和设计流程的现场可编程门阵列

    公开(公告)号：US20150109024A1

    公开(公告)日：2015-04-23

    申请号：US14060253

    申请日：2013-10-22

    申请人： Mohamed Saied Abdelfattah ,  Vaughn Timothy Betz

    发明人： Mohamed Saied Abdelfattah ,  Vaughn Timothy Betz

    IPC分类号： G06F17/50 ,  H03K19/0175

    CPC分类号： G06F17/5054 ,  H03K19/017581

    摘要： An enhanced field programmable gate-array (FPGA) incorporates one or more programmable networks-on-chip (NoCs) or NoC components integrated within the FPGA fabric. This NoC interconnect augments the existing FPGA interconnect. In one embodiment, the NoC is used as system-level interconnect to connect compute and communication modules to one another and integrate large systems on the FPGA. The NoC components include a “fabric port”, which is a configurable interface that bridges both data width and frequency between the embedded NoC routers and the FPGA fabric components such as logic blocks, block memory, multipliers, processors or I/Os. Finally, the FPGA design flow is modified to target the embedded NoC components either manually through designer intervention, or automatically.

    摘要翻译： 增强型现场可编程门阵列（FPGA）在FPGA架构中集成了一个或多个可编程片上（NoC）可编程网络或NoC组件。 这种NoC互连增强了现有的FPGA互连。 在一个实施例中，NoC用作系统级互连以将计算和通信模块彼此连接并且将大型系统集成在FPGA上。 NoC组件包括一个“Fabric端口”，它是一个可配置的接口，用于桥接嵌入式NoC路由器与FPGA架构组件（如逻辑块，块存储器，乘法器，处理器或I / O）之间的数据宽度和频率。 最后，FPGA设计流程被修改为通过设计者干预手动或自动定位嵌入式NoC组件。