SECURE CREDENTIALS CONTROL METHOD
    1.
    发明申请
    SECURE CREDENTIALS CONTROL METHOD 审中-公开
    安全证书控制方法

    公开(公告)号:US20090064297A1

    公开(公告)日:2009-03-05

    申请号:US12201150

    申请日:2008-08-29

    IPC分类号: H04L9/32 G06F21/00

    摘要: Methods, apparatus, and systems are provided to secure access to an account of a user. The account may have a system administrator. The user may have a credential for accessing the secure data on the account. The methods, apparatus, and systems involve setting a universal reset credential associated with the account, denying the system administrator of the account permission to change the first credential of the access feature, and permitting the system administrator to reset the access feature from the first credential to the universal reset credential.

    摘要翻译: 提供了方法,装置和系统以保护对用户帐户的访问。 该帐户可能有系统管理员。 用户可以具有用于访问账户上的安全数据的证书。 所述方法,装置和系统涉及设置与所述帐户相关联的通用重置凭证,拒绝所述帐户的系统管理员许可以更改所述访问特征的所述第一凭证,并允许所述系统管理员从所述第一凭证重置所述访问特征 到通用复位凭证。

    Stackable interconnection socket
    2.
    发明授权
    Stackable interconnection socket 失效
    可堆叠互连插座

    公开(公告)号:US5429511A

    公开(公告)日:1995-07-04

    申请号:US241510

    申请日:1994-05-12

    IPC分类号: H05K7/10 H01R13/72

    CPC分类号: H05K7/1023

    摘要: A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board. An extraction tool facilitates disengagement of the assembly from the second package mounted on the printed circuit board.

    摘要翻译: 公开了用于对准和配合集成电路(IC)封装的紧密间隔的引线的部件载体和配合系统,其保护集成电路封装并且允许容易的安装。 该系统特别适用于对准和配对具有高引脚数的集成电路。 载体组件对准用于配合和互连至少两个具有从封装延伸的多个引线的集成电路封装。 保护罩覆盖堆叠的包装,以使包装保持电气和机械接合,并确保集成电路封装不发生损坏。 在一个实施例中,第一包装被安装在承载器组件上并与保护罩耦合以形成预接合组件,然后将预接合组件与安装在印刷电路板上的第二封装接合。 提取工具有助于组件与安装在印刷电路板上的第二封装分离。

    Secure email communication system
    3.
    发明授权
    Secure email communication system 有权
    安全的电子邮件通信系统

    公开(公告)号:US08379867B2

    公开(公告)日:2013-02-19

    申请号:US12237258

    申请日:2008-09-24

    IPC分类号: H04L9/08

    摘要: The present invention provides a method and system for securing a digital data stream. A first key of a first asymmetric key pair from a key store remote from a host node is received at the host node. A dynamically generated key is received at the host node, which is used to encipher the digital data stream. The dynamically generated key is enciphered with the first key of the first asymmetric key pair. The enciphered digital data stream and the enciphered dynamically generated key are stored remotely from the host node and the key store.

    摘要翻译: 本发明提供一种用于保护数字数据流的方法和系统。 在主机节点处接收来自远离主机节点的密钥存储库的第一非对称密钥对的第一密钥。 在主机节点处接收动态生成的密钥,用于加密数字数据流。 动态生成的密钥用第一个非对称密钥对的第一个密钥加密。 加密的数字数据流和加密的动态生成的密钥从主机节点和密钥存储器远程存储。

    Integrated circuit extraction tool
    4.
    发明授权
    Integrated circuit extraction tool 失效
    集成电路提取工具

    公开(公告)号:US5617628A

    公开(公告)日:1997-04-08

    申请号:US357482

    申请日:1994-12-16

    IPC分类号: H01R43/26 H05K7/10 H05K13/00

    摘要: An integrated circuit extraction tool for extracting sockets or microprocessors having a staggered pin grid array (SPGA) pin arrangement. Such tool includes an elongated base having a first end and a second end, each end forming a set of teeth that permit entry and extension of the teeth, diagonally, through the staggered pins of the socket or microprocessor. In the preferred embodiment, the first end is disposed at ninety degree with respect to the elongated base. Further, the elongated base is formed with a curvature to enhance the leverage action necessary for an extraction operation.

    摘要翻译: 一种用于提取具有交错引脚格栅阵列(SPGA)引脚布置的插座或微处理器的集成电路提取工具。 这种工具包括具有第一端和第二端的细长底座,每个端部形成一组齿,允许齿对角地穿过插座或微处理器的交错销进入和伸出。 在优选实施例中,第一端相对于细长基座设置为九十度。 此外,细长基部形成有曲率以增强提取操作所需的杠杆作用。

    Stackable interconnection socket
    5.
    发明授权
    Stackable interconnection socket 失效
    可堆叠互连插座

    公开(公告)号:US5318451A

    公开(公告)日:1994-06-07

    申请号:US8208

    申请日:1993-01-25

    IPC分类号: H05K7/10 H01R23/72

    CPC分类号: H05K7/1023

    摘要: A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board. An extraction tool facilitates disengagement of the assembly from the second package mounted on the printed circuit board.

    摘要翻译: 公开了用于对准和配合集成电路(IC)封装的紧密间隔的引线的部件载体和配合系统,其保护集成电路封装并且允许容易的安装。 该系统特别适用于对准和配对具有高引脚数的集成电路。 载体组件对准用于配合和互连至少两个具有从封装延伸的多个引线的集成电路封装。 保护罩覆盖堆叠的包装,以使包装保持电气和机械接合,并确保集成电路封装不发生损坏。 在一个实施例中,第一包装被安装在承载器组件上并与保护罩耦合以形成预接合组件,然后将预接合组件与安装在印刷电路板上的第二封装接合。 提取工具有助于组件与安装在印刷电路板上的第二封装分离。

    Cloud computing appliance
    7.
    发明申请
    Cloud computing appliance 审中-公开
    云计算设备

    公开(公告)号:US20110289310A1

    公开(公告)日:2011-11-24

    申请号:US13112931

    申请日:2011-05-20

    IPC分类号: H04L9/00

    摘要: A cloud computing appliance is provided in exemplary embodiment. The cloud computing device includes a computer server. The computer server is configured to receive a user file having a user filename and a user data content. The computer server is further configured to record an index record for the user file including the user filename and a dynamically generated storage name. The computer server is further configured to encipher the user data content with a symmetric key, encipher the symmetric key with an asymmetric key, and transmit a cloud file having a filename of the dynamically generated storage name and a data content of the enciphered user data content and the enciphered symmetric key.

    摘要翻译: 在示例性实施例中提供了云计算设备。 云计算设备包括计算机服务器。 计算机服务器被配置为接收具有用户文件名和用户数据内容的用户文件。 计算机服务器还被配置为记录用户文件的索引记录,包括用户文件名和动态生成的存储名。 计算机服务器还被配置为用对称密钥加密用户数据内容,用非对称密钥加密对称密钥,并发送具有动态生成的存储名称的文件名的云文件和加密的用户数据内容的数据内容 和加密对称密钥。

    SECURE EMAIL COMMUNICATION SYSTEM
    8.
    发明申请
    SECURE EMAIL COMMUNICATION SYSTEM 有权
    安全电子邮件通信系统

    公开(公告)号:US20090080650A1

    公开(公告)日:2009-03-26

    申请号:US12237258

    申请日:2008-09-24

    IPC分类号: H04L9/06

    摘要: The present invention provides a method and system for securing a digital data stream. A first key of a first asymmetric key pair from a key store remote from a host node is received at the host node. A dynamically generated key is received at the host node, which is used to encipher the digital data stream. The dynamically generated key is enciphered with the first key of the first asymmetric key pair. The enciphered digital data stream and the enciphered dynamically generated key are stored remotely from the host node and the key store.

    摘要翻译: 本发明提供一种用于保护数字数据流的方法和系统。 在主机节点处接收来自远离主机节点的密钥存储库的第一非对称密钥对的第一密钥。 在主机节点处接收动态生成的密钥,用于加密数字数据流。 动态生成的密钥用第一个非对称密钥对的第一个密钥加密。 加密的数字数据流和加密的动态生成的密钥从主机节点和密钥存储器远程存储。

    Cache coherency without bus master arbitration signals
    9.
    发明授权
    Cache coherency without bus master arbitration signals 失效
    高速缓存一致性无总线主控仲裁信号

    公开(公告)号:US5724549A

    公开(公告)日:1998-03-03

    申请号:US131043

    申请日:1993-10-01

    IPC分类号: G06F12/08 G06F13/00

    CPC分类号: G06F12/0831

    摘要: A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or are not exclusively relied on by the processor-cache to assure validity of the data in the cache (e.g., a 386-bus compatible computer system using an external secondary cache in which bus arbitration signals are only connected to and used by the secondary cache controller). In an exemplary external-chip implementation, the cache coherency system (120) comprises two PLAs--a FLUSH module (122) and a WAVESHAPING module (124). The FLUSH module (a) receives selected bus cycle definition and control signals from a microprocessor ((110), (b) detects FLUSH (cache invalidation) conditions, i.e., bus master synchronization events, and for each such FLUSH condition, (c) provides a FLUSH output signal. The WAVESHAPING module provides a corresponding CPU/FLUSH signal to the microprocessor with the appropriate set up and hold time. The exemplary bus master synchronization events, or FLUSH conditions, that cause cache invalidation are: (a) hardware generated interrupts, and (b) read or read/write accesses to I/O address space, except for those directed to a hard disk or an external coprocessor. If the bus architecture uses memory-mapped I/O, accesses to selected regions of memory-mapped I/O space could also be used. The cache coherency functionality could be implemented on-board the microprocessor.

    摘要翻译: 公开了一种用于计算机系统的异步过程之间的数据通信的方法,其结合用于多主计算机系统中使用的处理器 - 高速缓存一致性系统,其中总线仲裁信号对于处理器高速缓存不可用,或 不完全依赖于处理器缓存来确保缓存中的数据的有效性(例如,使用外部二级高速缓存的386总线兼容的计算机系统,其中总线仲裁信号仅连接到二级缓存控制器并由二级缓存控制器使用 )。 在示例性的外部芯片实现中,高速缓存一致性系统(120)包括两个PLA-FLUSH模块(122)和WAVESHAPING模块(124)。 FLUSH模块(a)从微处理器接收所选择的总线周期定义和控制信号((110),(b)检测FLUSH(高速缓存无效)条件,即总线主同步事件,以及每个这样的FLUSH条件,(c) 提供FLUSH输出信号,WAVESHAPING模块在相应的设置和保持时间内为微处理器提供相应的CPU / FLUSH信号,导致高速缓存无效的示例性总线主站同步事件或FLUSH条件是:(a)硬件产生 中断和(b)对I / O地址空间的读/写访问,除了定向到硬盘或外部协处理器的访问,如果总线架构使用存储器映射I / O,则访问所选择的存储区域 也可以使用映射的I / O空间。高速缓存一致性功能可以在微处理器上实现。

    Integrated circuit extraction tool
    10.
    发明授权
    Integrated circuit extraction tool 失效
    集成电路提取工具

    公开(公告)号:US5440803A

    公开(公告)日:1995-08-15

    申请号:US63134

    申请日:1993-05-17

    IPC分类号: H01R43/26 H05K7/10 H05K13/00

    摘要: An integrated circuit extraction tool includes an elongated base having a first end and second end. A first set of teeth are provided on the first end and a second set of teeth are provided on the second end. The first set of teeth are spaced at a first spacing distance and the second set of teeth are spaced at a second spacing distance. In the preferred embodiment, the first set of teeth are spaced to correspond with the spacing between pins of a integrated circuit to be extracted and the second set of teeth are spaced at a distance to correspond to the spacing between base portions of a socket's connectors. One or both of the ends may be angled at ninety degrees to allow integrated circuit removal with minimal clearance.

    摘要翻译: 集成电路提取工具包括具有第一端和第二端的细长底座。 第一组齿设置在第一端上,第二组齿设置在第二端上。 第一组齿以第一间隔距离间隔开,并且第二组齿以第二间隔距离隔开。 在优选实施例中,第一组齿间隔开以与要提取的集成电路的引脚之间的间隔相对应,并且第二组齿间隔开一定距离以对应于插座连接器的基部之间的间隔。 一个或两个端部可以成90°角度,以允许以最小的间隙去除集成电路。