Integrated reverse battery protection circuit for an external MOSFET switch
    1.
    发明申请
    Integrated reverse battery protection circuit for an external MOSFET switch 有权
    用于外部MOSFET开关的集成反向电池保护电路

    公开(公告)号:US20060126245A1

    公开(公告)日:2006-06-15

    申请号:US11015315

    申请日:2004-12-15

    IPC分类号: H02H3/18

    CPC分类号: H02H11/002

    摘要: A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse battery condition is disclosed herein. This reverse battery protection circuit minimizes power consumption during a reverse battery event wherein there is no need for mechanical adjustments such as heat sinking and clamping to extract the heat away from the silicon and not destroy the device. Specifically, the reverse battery protection circuit includes a push-pull gate drive circuit coupled between the first and second power supply rail. A protection subcircuit portion connects between a first output node and the second power supply rail to turn the external FET ‘on’ during the reverse battery condition. In particular, the protection subcircuit portion connects to the external FET device and includes a p-channel device connected between a second output node that biases the external FET device and a first diode. A resistor connects between a first output node of the reverse battery protection circuit to provide a voltage drop between the drain terminal and the gate of the p-channel device. A second diode connects between the gate and the source of the p-channel device. In addition, a clamping circuit connects between the second output node and the third output node to provide clamping in the instance where the voltage at the second output node momentarily rises too high.

    摘要翻译: 本文公开了一种反向电池保护电路,其在反向电池状态期间提供用于保护外部NMOS开关的集成反向电池状态解决方案。 这种反向电池保护电路在反向电池事件期间最小化功率消耗,其中不需要机械调节,例如散热和夹紧,以将热量从硅提取出来,而不会破坏设备。 具体地,反向电池保护电路包括耦合在第一和第二电源轨之间的推挽栅极驱动电路。 保护子电路部分连接在第一输出节点和第二电源轨道之间,以在反向电池状态期间使外部FET“接通”。 特别地,保护子电路部分连接到外部FET器件,并且包括连接在偏置外部FET器件的第二输出节点和第一二极管之间的p沟道器件。 电阻器连接在反向电池保护电路的第一输出节点之间,以在漏极端子和p沟道器件的栅极之间提供电压降。 第二个二极管连接在p沟道器件的栅极和源极之间。 此外,钳位电路连接在第二输出节点和第三输出节点之间,以在第二输出节点处的电压瞬间上升得过高的情况下提供钳位。

    Full backside etching for pressure sensing silicon
    2.
    发明申请
    Full backside etching for pressure sensing silicon 有权
    用于压力感测硅的全面背面蚀刻

    公开(公告)号:US20070004207A1

    公开(公告)日:2007-01-04

    申请号:US11171939

    申请日:2005-06-30

    IPC分类号: H01L21/302

    摘要: The formation of a semiconductor sensing device is disclosed, where the device can be used to sense pressure, for example. The device is formed by etching the entire backside of a semiconductor substrate or wafer. This streamlines the fabrication process by omitting a number of steps that would otherwise be required to selectively etch certain locations of the substrate. This also improves device performance and compactness by allowing associated support circuitry to be formed closer to a sensing region, and more particularly piezoelectric elements of the sensing region.

    摘要翻译: 公开了半导体感测装置的形成,其中例如可以使用该装置感测压力。 该器件通过蚀刻半导体衬底或晶片的整个背面而形成。 这通过省略了选择性地蚀刻衬底的某些位置所需要的许多步骤来简化制造工艺。 这还通过允许相关联的支持电路形成为更接近感测区域,更具体地,感测区域的压电元件,来提高设备性能和紧凑性。