公开(公告)号：US20060126245A1

公开(公告)日：2006-06-15

申请号：US11015315

申请日：2004-12-15

申请人： William Grose ,  Timothy Legat ,  Sanmukh Patel

发明人： William Grose ,  Timothy Legat ,  Sanmukh Patel

IPC分类号： H02H3/18

CPC分类号： H02H11/002

摘要： A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse battery condition is disclosed herein. This reverse battery protection circuit minimizes power consumption during a reverse battery event wherein there is no need for mechanical adjustments such as heat sinking and clamping to extract the heat away from the silicon and not destroy the device. Specifically, the reverse battery protection circuit includes a push-pull gate drive circuit coupled between the first and second power supply rail. A protection subcircuit portion connects between a first output node and the second power supply rail to turn the external FET ‘on’ during the reverse battery condition. In particular, the protection subcircuit portion connects to the external FET device and includes a p-channel device connected between a second output node that biases the external FET device and a first diode. A resistor connects between a first output node of the reverse battery protection circuit to provide a voltage drop between the drain terminal and the gate of the p-channel device. A second diode connects between the gate and the source of the p-channel device. In addition, a clamping circuit connects between the second output node and the third output node to provide clamping in the instance where the voltage at the second output node momentarily rises too high.

摘要翻译： 本文公开了一种反向电池保护电路，其在反向电池状态期间提供用于保护外部NMOS开关的集成反向电池状态解决方案。 这种反向电池保护电路在反向电池事件期间最小化功率消耗，其中不需要机械调节，例如散热和夹紧，以将热量从硅提取出来，而不会破坏设备。 具体地，反向电池保护电路包括耦合在第一和第二电源轨之间的推挽栅极驱动电路。 保护子电路部分连接在第一输出节点和第二电源轨道之间，以在反向电池状态期间使外部FET“接通”。 特别地，保护子电路部分连接到外部FET器件，并且包括连接在偏置外部FET器件的第二输出节点和第一二极管之间的p沟道器件。 电阻器连接在反向电池保护电路的第一输出节点之间，以在漏极端子和p沟道器件的栅极之间提供电压降。 第二个二极管连接在p沟道器件的栅极和源极之间。 此外，钳位电路连接在第二输出节点和第三输出节点之间，以在第二输出节点处的电压瞬间上升得过高的情况下提供钳位。

公开(公告)号：US20070168776A1

公开(公告)日：2007-07-19

申请号：US11243898

申请日：2005-10-04

申请人： William Grose ,  Lonnie Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

发明人： William Grose ,  Lonnie Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C16/04 ,  G11C29/48 ,  G11C2029/3202

摘要： Systems, methods and circuits for implementing efficient device testing. As one example, a method is disclosed for testing a device that includes both a digital and analog portion. In some cases, the digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch, devices, and is controlled by a selector input. In the method, a load clock is applied to the plurality of latch devices such that a pattern is loaded into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.

摘要翻译： 用于实现高效设备测试的系统，方法和电路。 作为一个示例，公开了一种用于测试包括数字和模拟部分的设备的方法。 在一些情况下，数字部分包括多个锁存装置，并且模拟部分包括多个存储器单元和多个选择器装置。 多个选择器装置中的每一个电耦合到相应的一个存储单元，至少间接耦合到多个锁存器件中的一个，并由选择器输入端控制。 在该方法中，将负载时钟施加到多个锁存装置，使得模式被加载到多个锁存装置中。 选择器输入被断言，使得图案的导数被多个选择器接收并返回到多个锁存装置。 系统时钟被施加到多个锁存装置，使得图案的导数被加载到多个锁存装置中。

公开(公告)号：US20060103432A1

公开(公告)日：2006-05-18

申请号：US11192969

申请日：2005-07-29

申请人： Suribhotla Rajasekhar ,  Hasibur Rahman ,  Alexander Teutsch ,  William Grose

发明人： Suribhotla Rajasekhar ,  Hasibur Rahman ,  Alexander Teutsch ,  William Grose

IPC分类号： G01R29/02

CPC分类号： H03K19/00346

摘要： A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.

摘要翻译： 去交点电路利用耦合到输入信号的第一触发器和耦合到电路的输出的第二触发器，其具有从输出到门的反馈以控制到第一触发器的第一和第二输入。 在替代方案中，在第一触发器的输出和第二触发器的输入之间提供一个计数器，以提供灵活性以及延迟延迟的可能性。

公开(公告)号：US20060100795A1

公开(公告)日：2006-05-11

申请号：US10985388

申请日：2004-11-09

申请人： Tobin Hagan ,  David Baldwin ,  William Grose

发明人： Tobin Hagan ,  David Baldwin ,  William Grose

IPC分类号： G01B5/28 ,  G01B5/30

CPC分类号： G01F1/698

摘要： A system and method are provided to regulate resistance in a discontinuous time hot-wire anemometer. The solution removes supply voltage dependency on the mass airflow output signal. Operating the hot-wire anemometer using discontinuous time regulation offers lower system power, but introduces an inverse supply dependent term in the associated transfer function. This effect is removed by multiplying the output signal via a supply dependent signal.

摘要翻译： 提供了一种用于调节不连续时间热线风速计中的电阻的系统和方法。 该解决方案消除了对质量气流输出信号的电源电压依赖性。 使用不连续时间调节操作热线风速计提供较低的系统功率，但在相关的传递函数中引入了逆供电相关项。 通过经由电源相关信号乘以输出信号来消除这种影响。

公开(公告)号：US20050179471A1

公开(公告)日：2005-08-18

申请号：US10777991

申请日：2004-02-12

申请人： MD Abidur Rahman ,  William Grose ,  Brett Smith

发明人： MD Abidur Rahman ,  William Grose ,  Brett Smith

IPC分类号： H03B1/00 ,  H03K17/0412

CPC分类号： H03K17/04123

摘要： The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface. The circuit also has a fifth transistor (216), coupled to a second voltage supply (218), to the first node, and to the output interface.

摘要翻译： 本发明提供一种用于控制输出驱动电路（206）的驱动信号定时参数的系统（200）。 本发明定义了具有输出接口（204）和耦合到第一电压源（230），第一控制信号（232）和第一节点（220）的第一晶体管（222）的驱动器电路。 电路还具有耦合在第一节点和第二节点（234）之间的第一电阻元件。 第二电阻元件（228）耦合到地。 第二晶体管（224）耦合到第二节点，耦合到第二控制信号（236）和第二电阻元件。 电路具有耦合到第一和第二节点以及耦合到第三节点（240）的第三晶体管（244）。 第三电阻元件（242）耦合在第三节点和输出接口之间。 第四晶体管（238）耦合到第一和第三节点以及输出接口。 电路还具有耦合到第二电压源（218）的第五晶体管（216）到第一节点和输出接口。

公开(公告)号：US20050007084A1

公开(公告)日：2005-01-13

申请号：US10680999

申请日：2003-10-08

申请人： Jingwei Xu ,  Zbigniew Lata ,  William Grose

发明人： Jingwei Xu ,  Zbigniew Lata ,  William Grose

IPC分类号： H02M3/156 ,  G05F1/40

CPC分类号： H02M3/156

摘要： System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch and filter block (SFB) (such as the SFB 510), a comparator (such as the comparator 520), and a fixed off time logic (FOTL) (such as the FOTL 525). The comparator compares an output voltage with a reference voltage. When the output voltage is equal to or exceeds the reference voltage, the comparator asserts a value on a signal line to the FOTL. The FOTL then shuts down the SFB for a specified period of time. During the off time, the output voltage decays. After the specified period of time expires, the SFB is turned back on and the output voltage can recharge. The duration of time that the SFB remains on is a function of the supply voltage, thus permitting an adjustable operating frequency.

摘要翻译： 用于提供具有可调工作频率范围的开关稳压器的系统。 优选实施例包括电压源和负载，开关和滤波器块（SFB）（例如SFB510），比较器（例如比较器520）和固定关断时间逻辑（FOTL）（诸如 FOTL 525）。 比较器将输出电压与参考电压进行比较。 当输出电压等于或超过参考电压时，比较器将在FOTL信号线上产生一个值。 FOTL然后关闭SFB一段指定的时间。 在关机时间内，输出电压衰减。 指定的时间段到期后，SFB再次接通，输出电压可以充值。 SFB保持导通的持续时间是电源电压的函数，从而允许可调节的工作频率。