公开(公告)号：US5469566A

公开(公告)日：1995-11-21

申请号：US402963

申请日：1995-03-10

Applicant: Gerald L. Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

Inventor： Gerald L. Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G11B20/1833 ,  G06F2211/1054

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs a switching circuit to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Abstract translation: 具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。 例如，这样的系统可以具有用于处理两组数据的两个通道。 奇偶生成技术采用切换电路来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。 奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。 本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。 对于某些系统应用，可能希望将RAM用作大型统一的FIFO。 因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

公开(公告)号：US5831393A

公开(公告)日：1998-11-03

申请号：US832050

申请日：1997-04-02

Applicant: Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

Inventor： Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

IPC: G06F11/10 ,  G11B20/18 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G11B20/1833 ,  G06F2211/1054

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Abstract translation: 具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。 例如，这样的系统可以具有用于处理两组数据的两个通道。 奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。 奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。 本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。 对于某些系统应用，可能希望将RAM用作大型统一的FIFO。 因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

公开(公告)号：US5675726A

公开(公告)日：1997-10-07

申请号：US555331

申请日：1995-11-08

Applicant: Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

Inventor： Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

IPC: G06F11/10 ,  G11B20/18 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G11B20/1833 ,  G06F2211/1054

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Abstract translation: 具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。 例如，这样的系统可以具有用于处理两组数据的两个通道。 奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。 奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。 本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。 对于某些系统应用，可能希望将RAM用作大型统一的FIFO。 因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。