公开(公告)号：US5831393A

公开(公告)日：1998-11-03

申请号：US832050

申请日：1997-04-02

Applicant: Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

Inventor： Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

IPC: G06F11/10 ,  G11B20/18 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G11B20/1833 ,  G06F2211/1054

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Abstract translation: 具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。 例如，这样的系统可以具有用于处理两组数据的两个通道。 奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。 奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。 本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。 对于某些系统应用，可能希望将RAM用作大型统一的FIFO。 因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

公开(公告)号：US5675726A

公开(公告)日：1997-10-07

申请号：US555331

申请日：1995-11-08

Applicant: Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

Inventor： Gerald Lee Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

IPC: G06F11/10 ,  G11B20/18 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G11B20/1833 ,  G06F2211/1054

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs switching means to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Abstract translation: 具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。 例如，这样的系统可以具有用于处理两组数据的两个通道。 奇偶产生技术采用切换装置来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。 奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。 本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。 对于某些系统应用，可能希望将RAM用作大型统一的FIFO。 因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

公开(公告)号：US07619984B2

公开(公告)日：2009-11-17

申请号：US11215894

申请日：2005-08-30

Applicant: Richard D. Carmichael

Inventor： Richard D. Carmichael

IPC: H04L12/26 ,  H04J3/00 ,  H04J3/07 ,  G06F11/00 ,  H03M13/00

CPC classification number: H04L1/1829 ,  H04L1/08 ,  H04L1/201

Abstract: A method for error handling of corrupted repeating primitives during frame reception is disclosed. The method comprises identifying a portion of a received frame including a repeating primitive sequence, determining whether data in the repeating primitive sequence has one or more errors, and indicating a successful reception of the received frame with the one or more errors in the repeating primitive sequence if the number of errors is less than a determined threshold. Other embodiments are also disclosed.

Abstract translation: 公开了一种在帧接收期间错误处理损坏的重复原语的方法。 该方法包括识别包括重复原语序列的接收帧的一部分，确定重复原语序列中的数据是否具有一个或多个错误，并且指示接收的帧的成功接收与重复的基本序列中的一个或多个错误 如果错误的数量小于确定的阈值。 还公开了其他实施例。

公开(公告)号：US07366958B2

公开(公告)日：2008-04-29

申请号：US11013033

申请日：2004-12-14

Applicant: Nathan E. Marushak ,  Roger C. Jeppsen ,  Richard C. Beckett ,  Devicharan Devidas ,  Richard D. Carmichael

Inventor： Nathan E. Marushak ,  Roger C. Jeppsen ,  Richard C. Beckett ,  Devicharan Devidas ,  Richard D. Carmichael

IPC: G06F11/00

CPC classification number: G06F13/385 ,  H04L1/0061 ,  H04L1/1874 ,  H04L1/1887 ,  H04L2001/0094

Abstract: One embodiment of a method may include, in response, at least in part, to one or more received frames, generating an interrupt and preventing transmission of one or more other frames. The one or more received frames may indicate, at least in part, an error condition or a commencement of a data transfer. The method of this embodiment also may include, in response, at least in part, to the interrupt, executing one or more instructions. The one or more instructions, when executed, may optionally result in deleting the one or more other frames, and if the one or more received frames indicate, at least in part, the error condition, commencing recovery from the error condition. If the one or more received frames indicate, at least in part, the commencement of the data transfer, the method of the embodiment may include storing data associated with the data transfer.

Abstract translation: 方法的一个实施例可以响应于至少部分地包括一个或多个接收的帧，产生中断并防止一个或多个其他帧的传输。 至少部分地，一个或多个接收到的帧可以指示错误状况或数据传送的开始。 该实施例的方法还可以响应于至少部分地包括执行一个或多个指令的中断。 一个或多个指令在执行时可以可选地导致删除一个或多个其他帧，并且如果一个或多个接收到的帧至少部分地指示错误状况，则从错误状态开始恢复。 如果一个或多个接收的帧至少部分地指示数据传输的开始，则该实施例的方法可以包括存储与数据传输相关联的数据。

公开(公告)号：US5469566A

公开(公告)日：1995-11-21

申请号：US402963

申请日：1995-03-10

Applicant: Gerald L. Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

Inventor： Gerald L. Hohenstein ,  Michael E. Nielson ,  Tin S. Tang ,  Richard D. Carmichael ,  William A. Brant

IPC: G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G11B20/1833 ,  G06F2211/1054

Abstract: A redundant array computer system having a high-speed CPU bus and lower-speed I/O buses, in which parity blocks are generated for a plurality of data blocks from multiple CPU bus logical channels in a randomly-interleaved manner to provide enhanced I/O transfer rates. For example, such a system may have two channels for processing two sets of data. The parity generation technique employs a switching circuit to switch channels on the CPU bus between the first set and the second set, generating parity information that can be transferred independently over two I/O buses. The parity generation technique achieves an effective I/O bus transfer rate more closely matched to the speed of the CPU bus. The invention shares a single XOR gate and related support circuitry between multiple logical channels by providing a configurable electronic memory, thus achieving economies in implementation. For certain system applications, it may be desirable to utilize the RAM as a large, unified FIFO. Thus, the system can be adapted to generate parity information for very large blocks of data in a single channel.

Abstract translation: 具有高速CPU总线和低速I / O总线的冗余阵列计算机系统，其中以随机交错方式从多个CPU总线逻辑信道为多个数据块生成奇偶校验块，以提供增强的I / O转移率。 例如，这样的系统可以具有用于处理两组数据的两个通道。 奇偶生成技术采用切换电路来切换第一组和第二组之间的CPU总线上的通道，产生可以通过两个I / O总线独立传输的奇偶校验信息。 奇偶生成技术实现了与CPU总线速度更接近的有效I / O总线传输速率。 本发明通过提供可配置的电子存储器来共享多个逻辑信道之间的单个XOR门和相关的支持电路，从而实现实现的经济性。 对于某些系统应用，可能希望将RAM用作大型统一的FIFO。 因此，该系统可以适于在单个信道中为非常大的数据块生成奇偶校验信息。

公开(公告)号：US5894560A

公开(公告)日：1999-04-13

申请号：US702998

申请日：1996-08-26

Applicant: Richard D. Carmichael ,  Joel M. Ward ,  Michael A. Winchell

Inventor： Richard D. Carmichael ,  Joel M. Ward ,  Michael A. Winchell

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC classification number: G06F13/28 ,  G06F13/122

Abstract: An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device's buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.

Abstract translation: 一种用于在多任务多线程操作系统的控制下改善计算机系统的输入/输出性能的装置和方法。 特别地，本发明提供了一种装置和方法，用于使用单个数据管理器，使用单个数据管理器链接用于信道0的PRD表的连续DMA散射收集子块，其具有用于信道1的PRD表的连续DMA散射收集子块，同时保持最大媒体 带宽。 基于来自I / O设备的缓冲存储器的数据的可用性来调度DMA块传输，从而最小化媒体或网络空闲时间以及最小化I / O总线空闲时间。 获得多个I / O总线及其相关设备的近最大总带宽。 因此，与先前技术相比，装置和方法提供了显着的性能优点，所述技术具有用单个数据管理器实现的两个I / O通道系统。

公开(公告)号：US5864712A

公开(公告)日：1999-01-26

申请号：US777858

申请日：1996-12-31

Applicant: Richard D. Carmichael ,  Joel M. Ward ,  Michael A. Winchell

Inventor： Richard D. Carmichael ,  Joel M. Ward ,  Michael A. Winchell

IPC: G06F13/28 ,  G06F13/10

CPC classification number: G06F13/28

Abstract: A method an corresponding apparatus for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to interleave contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a first I/O channel with contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a second I/O channel, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled by the single data manager based on the availability of data from the I/O devices' buffer memories, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager. The apparatus and methods of the present invention are also extended to encompass a plurality "n" of data managers interleaving contiguous block transfers among a larger plurality "n+i" of I/O devices.

Abstract translation: 一种用于在多任务多线程操作系统的控制下改善计算机系统的输入/输出性能的相应装置的方法。 特别地，本发明提供了一种装置和方法，用于将与第一I / O通道相对应的PRD表的连续的DMA散射/采集子块交织到与第二I / O对应的PRD表的连续DMA散射/收集子块 通道，使用单个数据管理器，同时保持最大的媒体带宽。 基于来自I / O设备的缓冲存储器的数据的可用性，单个数据管理器调度DMA块传输，从而最小化媒体或网络空闲时间以及最小化I / O总线空闲时间。 获得多个I / O总线及其相关设备的近最大总带宽。 因此，与先前技术相比，装置和方法提供了显着的性能优点，所述技术具有用单个数据管理器实现的两个I / O通道系统。 本发明的装置和方法还被扩展为包含多个“n”个数据管理器，在I / O设备的较大的多个“n + i”之间交织连续块传输。