公开(公告)号：US20120313172A1

公开(公告)日：2012-12-13

申请号：US13489128

申请日：2012-06-05

申请人： Masaharu MATSUDAIRA ,  Toshiharu Nagumo ,  Hiroshi Takeda ,  Kiyoshi Takeuchi

发明人： Masaharu MATSUDAIRA ,  Toshiharu Nagumo ,  Hiroshi Takeda ,  Kiyoshi Takeuchi

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/20 ,  H01L29/02

CPC分类号： H01L27/1203 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/78648

摘要： This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively.

摘要翻译： 本发明提供一种具有减小的晶体管特性变化的半导体器件。 半导体器件具有SOI衬底，第一元件隔离绝缘层，第一和第二导电型晶体管以及第一和第二后栅极触点。 SOI衬底具有具有第一和第二导电类型层，绝缘层和半导体层的半导体衬底。 第一元件隔离绝缘层被埋在SOI衬底中，具有到达第一导电类型层的下端，并且将第一元件区域与第二元件区域隔离。 第一和第二导电类型晶体管分别位于第一和第二元件区域中，并且在半导体层中形成有各自的沟道区。 第一和第二背栅极触点分别耦合到第一和第二元件区域中的第二导电类型层。

公开(公告)号：US20120065920A1

公开(公告)日：2012-03-15

申请号：US13222019

申请日：2011-08-31

申请人： Toshiharu NAGUMO ,  Kiyoshi TAKEUCHI

发明人： Toshiharu NAGUMO ,  Kiyoshi TAKEUCHI

IPC分类号： G06F19/00 ,  G01R31/02

CPC分类号： G01R31/2621

摘要： An evaluation method of a semiconductor device according to an aspect of the present invention includes MISFETs including a gate insulating film, the evaluation method including measuring an RTN of a plurality of MISFETs, and extracting at least two parameters selected from a position of a trap in the gate insulating film, an energy of the trap, an RTN time constant, and an RTN amplitude based on a measurement result of the RTN, and obtaining a correlation between these at least two parameters.

摘要翻译： 根据本发明的一个方面的半导体器件的评估方法包括具有栅极绝缘膜的MISFET，所述评估方法包括测量多个MISFET的RTN，以及从陷阱的位置中提取至少两个参数 栅极绝缘膜，阱的能量，RTN时间常数和基于RTN的测量结果的RTN振幅，并且获得这些至少两个参数之间的相关性。