公开(公告)号：US12125923B2

公开(公告)日：2024-10-22

申请号：US17191173

申请日：2021-03-03

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jaroslav Pjencak ,  Moshe Agam ,  Johan Camiel Julia Janssens

IPC分类号： H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/861 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/76291 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/6609 ,  H01L29/7824

摘要： A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.

公开(公告)号：US12074057B2

公开(公告)日：2024-08-27

申请号：US18057688

申请日：2022-11-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/762 ,  G06F30/392 ,  H01L21/84 ,  H01L29/06

CPC分类号： H01L21/76283 ,  H01L21/845 ,  H01L29/0649 ,  G06F30/392

摘要： Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over the first well. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.

公开(公告)号：US20240234448A1

公开(公告)日：2024-07-11

申请号：US18151509

申请日：2023-01-09

申请人： GlobalFoundries U.S. Inc.

发明人： DAVID PRITCHARD ,  HONG YU ,  ZHIXING ZHAO

IPC分类号： H01L27/13 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/13 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor device is provided. The semiconductor device includes a substrate, a gate electrode, an isolation structure, and an electrode plate. The gate electrode is over the substrate and the isolation structure is in contact with the gate electrode. The electrode plate is in the isolation structure.

公开(公告)号：US12027526B2

公开(公告)日：2024-07-02

申请号：US17949266

申请日：2022-09-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC分类号： H01L27/12 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238

摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US11923239B2

公开(公告)日：2024-03-05

申请号：US17663898

申请日：2022-05-18

申请人： Soitec

发明人： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L21/76283 ,  H01L21/02002 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/78603 ,  H01L21/76264

摘要： Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：US20240071812A1

公开(公告)日：2024-02-29

申请号：US17823508

申请日：2022-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Lei Chen ,  Anhao Cheng ,  Meng-I Kang ,  Yen-Liang Lin

IPC分类号： H01L21/762 ,  H01L21/84

CPC分类号： H01L21/76275 ,  H01L21/76283 ,  H01L21/84

摘要： A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.

公开(公告)号：US20240006532A1

公开(公告)日：2024-01-04

申请号：US18465050

申请日：2023-09-11

申请人： Acorn Semi, LLC

发明人： Paul A. Clifton ,  Andreas Goebel

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/7849 ,  H01L29/0649 ,  H01L27/1203 ,  H01L21/76283 ,  H01L21/02381 ,  H01L21/76254 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7846 ,  H01L29/105

摘要： A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

公开(公告)号：US11798836B2

公开(公告)日：2023-10-24

申请号：US17350930

申请日：2021-06-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Yu Yang ,  Po-Wei Liu ,  Yun-Chi Wu ,  Yu-Wen Tseng ,  Chia-Ta Hsieh ,  Ping-Cheng Li ,  Tsung-Hua Yang ,  Yu-Chun Chang

IPC分类号： H01L21/762 ,  H01L21/74 ,  H01L23/535

CPC分类号： H01L21/76283 ,  H01L21/743 ,  H01L23/535

摘要： A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

公开(公告)号：US11791411B2

公开(公告)日：2023-10-17

申请号：US17657854

申请日：2022-04-04

申请人： Acorn Semi, LLC

发明人： Paul A. Clifton ,  Andreas Goebel

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76254 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848

摘要： A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

公开(公告)号：US11764105B2

公开(公告)日：2023-09-19

申请号：US17747274

申请日：2022-05-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chia-Hsiang Hsu

IPC分类号： H01L21/762 ,  H01L27/06 ,  H10B51/30

CPC分类号： H01L21/76283 ,  H01L21/76224 ,  H01L27/0629 ,  H10B51/30

摘要： A semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer disposed over the semiconductor substrate, and a silicon layer disposed over the buried oxide layer. The semiconductor device structure also includes a first shallow trench isolation (STI) structure penetrating through the silicon layer and the buried oxide layer and extending into the semiconductor substrate. The first STI structure includes a first liner contacting the semiconductor substrate and the silicon layer, a second liner covering the first liner and contacting the buried oxide layer, and a third liner covering the second liner. The first liner, the second liner and the third liner are made of different materials. The first STI structure also includes a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.