公开(公告)号：US20080005296A1

公开(公告)日：2008-01-03

申请号：US11430116

申请日：2006-05-08

Applicant: William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

Inventor： William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

IPC: G06F15/173

CPC classification number: H04L47/20 ,  H04L49/901 ,  H04L67/28

Abstract: Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

Abstract translation: 用于同步数据的使用的技术，例如通过网络发送的分组，包括接收指示由DMA控制器拥有的特定缓冲器描述符的专用索引数据，用于在数据端口和对应的存储器缓冲器之间移动数据。 写命令被放置在存储器交换队列上，以将所有者更改为不同的处理器，并且私有索引数据被递增。 确定公共索引，其指示所有者最近更改为处理器并且已知对于处理器可见的不同缓冲器描述符。 响应于从处理器接收到更改为处理器所有权的最新缓冲器描述符的请求，将公共索引数据发送到处理器。 基于公共索引数据，处理器与保证由处理器拥有的缓冲区描述符交换数据。

公开(公告)号：US20070294694A1

公开(公告)日：2007-12-20

申请号：US11454820

申请日：2006-06-16

Applicant: Robert Jeter ,  Trevor Gamer ,  William Lee ,  Scott Smith ,  Gegory Goss

Inventor： Robert Jeter ,  Trevor Gamer ,  William Lee ,  Scott Smith ,  Gegory Goss

IPC: G06F9/46

CPC classification number: G06F9/462 ,  G06F9/30123 ,  G06F9/3851

Abstract: Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2c registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2T threads. A particular register is accessed in a register bank that has 2(C+T) registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.

Abstract translation: 用于处理共享核心处理器的多个线程中的每一个的技术包括从核心处理器接收线程内注册地址。 该地址包含用于访问每个线程的2个C / S寄存器中的每一个的C位。 从核心处理器外部的线程调度程序接收线程ID。 线程ID包含用于指示最多2条线程的特定线程的T位。 使用包括线程间寄存器地址和线程ID的线程间地址的寄存器组中访问具有2个（C + T）寄存器的特定寄存器。 特定的寄存器保存具有线程ID的线程的线程内注册地址的内容。 因此，所有线程的所有寄存器的寄存器内容都驻留在寄存器组中。 线程切换通过简单地访问寄存器组中的不同切片而快速完成，而不会在一组寄存器和存储器之间交换内容。

公开(公告)号：US08041929B2

公开(公告)日：2011-10-18

申请号：US11454820

申请日：2006-06-16

Applicant: Robert Jeter ,  Trevor Gamer ,  William Lee ,  Scott Smith ,  Gegory Goss

Inventor： Robert Jeter ,  Trevor Gamer ,  William Lee ,  Scott Smith ,  Gegory Goss

IPC: G06F9/40 ,  G06F9/46

CPC classification number: G06F9/462 ,  G06F9/30123 ,  G06F9/3851

Abstract: Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2c registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2T threads. A particular register is accessed in a register bank that has 2(C+T) registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.

Abstract translation: 用于处理共享核心处理器的多个线程中的每一个的技术包括从核心处理器接收线程内注册地址。 该地址包含用于访问每个线程的每个2c寄存器的C位。 从核心处理器外部的线程调度程序接收线程ID。 线程ID包含用于指示最多2T线程的特定线程的T位。 在具有2（C + T）个寄存器的寄存器组中访问特定寄存器，该寄存器使用包括线程内寄存器地址和线程ID的线程间地址。 特定的寄存器保存具有线程ID的线程的线程内注册地址的内容。 因此，所有线程的所有寄存器的寄存器内容都驻留在寄存器组中。 线程切换通过简单地访问寄存器组中的不同切片而快速完成，而不会在一组寄存器和存储器之间交换内容。

公开(公告)号：US07461180B2

公开(公告)日：2008-12-02

申请号：US11430116

申请日：2006-05-08

Applicant: William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

Inventor： William Lee ,  Trevor Gamer ,  Martin Hughes ,  Dennis Briddell

IPC: G05F13/00 ,  G06F15/173

CPC classification number: H04L47/20 ,  H04L49/901 ,  H04L67/28

Abstract: Techniques for synchronizing use of buffer descriptors for data, such as packets transmitted over a network, include receiving private index data that indicates a particular buffer descriptor owned by a DMA controller, for moving data between a data port and a corresponding memory buffer. A write command is placed on a memory exchange queue to change the owner to a different processor and the private index data is incremented. A public index is determined, which indicates a different buffer descriptor in which the owner is most recently changed to the processor and is known to be visible to the processor. In response to receiving a request from the processor for the most recent buffer descriptor changed to processor ownership, the public index data is sent to the processor. Based on the public index data, the processor exchanges data with buffer descriptors guaranteed to be owned by the processor.

Abstract translation: 用于同步数据的使用的技术，例如通过网络发送的分组，包括接收指示由DMA控制器拥有的特定缓冲器描述符的专用索引数据，用于在数据端口和对应的存储器缓冲器之间移动数据。 写命令被放置在存储器交换队列上，以将所有者更改为不同的处理器，并且私有索引数据被递增。 确定公共索引，其指示所有者最近更改为处理器并且已知对于处理器可见的不同缓冲器描述符。 响应于从处理器接收到更改为处理器所有权的最新缓冲器描述符的请求，将公共索引数据发送到处理器。 基于公共索引数据，处理器与保证由处理器拥有的缓冲区描述符交换数据。