公开(公告)号：US07781859B2

公开(公告)日：2010-08-24

申请号：US12054224

申请日：2008-03-24

申请人： Puo-Yu Chiang ,  Tsai Chun Lin ,  Chih-Wen (Albert) Yao ,  David Ho

发明人： Puo-Yu Chiang ,  Tsai Chun Lin ,  Chih-Wen (Albert) Yao ,  David Ho

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L29/0623 ,  H01L29/0649

摘要： An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的阱区; 在所述阱区上的含金属层，其中所述含金属层和所述阱区形成肖特基势垒; 围绕所述含金属层的隔离区域; 以及在金属含有层下面与第一导电类型相反的第二导电类型的深阱区域。 深井区具有至少一部分与含金属层的一部分垂直重叠的部分。 深阱区域与隔离区域垂直间隔开，并且阱区域与金属含量层垂直间隔开。

公开(公告)号：US20090236679A1

公开(公告)日：2009-09-24

申请号：US12054224

申请日：2008-03-24

申请人： Puo-Yu Chiang ,  Tsai Chun Lin ,  Chih-Wen Albert Yao ,  David Ho

发明人： Puo-Yu Chiang ,  Tsai Chun Lin ,  Chih-Wen Albert Yao ,  David Ho

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0623 ,  H01L29/0649

摘要： An integrated circuit structure includes a semiconductor substrate; a well region of a first conductivity type over the semiconductor substrate; a metal-containing layer on the well region, wherein the metal-containing layer and the well region form a Schottky barrier; an isolation region encircling the metal-containing layer; and a deep-well region of a second conductivity type opposite the first conductivity type under the metal-containing layer. The deep-well region has at least a portion vertically overlapping a portion of the metal-containing layer. The deep-well region is vertically spaced apart from the isolation region and the metal-containing layer by the well region.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的阱区; 在所述阱区上的含金属层，其中所述含金属层和所述阱区形成肖特基势垒; 围绕所述含金属层的隔离区域; 以及在金属含有层下面与第一导电类型相反的第二导电类型的深阱区域。 深井区具有至少一部分与含金属层的一部分垂直重叠的部分。 深阱区域与隔离区域垂直间隔开，并且阱区域由金属含有层垂直间隔开。

公开(公告)号：US20080157197A1

公开(公告)日：2008-07-03

申请号：US11646683

申请日：2006-12-28

申请人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

发明人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66659

摘要： A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括覆盖衬底的第一导电类型的第一阱区，覆盖衬底并且横向邻接第一阱区的与第一导电类型相反的第二导电类型的第二阱区，第二阱的第二阱区 类型相邻并且与第一阱区间隔开，第二导电类型的第一深阱区域位于第一阱区域和第二阱区域的至少一部分的下面，第二阱区域的第二深阱区域位于第三阱区域下面，以及 与第一深阱区间隔开，第一阱区域中的绝缘区域，从绝缘区域延伸到第二阱区域上方的栅极电介质，以及栅极电介质上的栅极电极。

公开(公告)号：US20090256200A1

公开(公告)日：2009-10-15

申请号：US12103524

申请日：2008-04-15

申请人： Chih-Wen (Albert) Yao ,  Puo-Yu Chiang ,  Tsai Chun Lin ,  Tsung-Yi Huang

发明人： Chih-Wen (Albert) Yao ,  Puo-Yu Chiang ,  Tsai Chun Lin ,  Tsung-Yi Huang

IPC分类号： H01L29/78

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二HVW区域与第一导电类型相反，覆盖在衬底上并横向邻接第一HVW区域; 从第一HVW区域延伸到第二HVW区域上方的栅极电介质; 栅电极上的栅电极; 第二HVW区域中的漏极区域; 栅极电介质的与漏极区相反的一侧的源极区; 以及位于第二HVW区域下方的第一导电类型的深阱区域。 基本上没有深沟区直接形成在漏极区下面。

公开(公告)号：US07928508B2

公开(公告)日：2011-04-19

申请号：US12103524

申请日：2008-04-15

申请人： Chih-Wen (Albert) Yao ,  Puo-Yu Chiang ,  Tsai Chun Lin ,  Tsung-Yi Huang

发明人： Chih-Wen (Albert) Yao ,  Puo-Yu Chiang ,  Tsai Chun Lin ,  Tsung-Yi Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/063 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second HVW region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first HVW region; a gate dielectric extending from over the first HVW region to over the second HVW region; a gate electrode on the gate dielectric; a drain region in the second HVW region; a source region at an opposite side of the gate dielectric than the drain region; and a deep well region of the first conductivity type underlying the second HVW region. Substantially no deep well region is formed directly underlying the drain region.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二HVW区域与第一导电类型相反，覆盖在衬底上并横向邻接第一HVW区域; 从第一HVW区域延伸到第二HVW区域上方的栅极电介质; 栅电极上的栅电极; 第二HVW区域中的漏极区域; 栅极电介质的与漏极区相反的一侧的源极区; 以及位于第二HVW区域下方的第一导电类型的深阱区域。 基本上没有深沟区直接形成在漏极区下面。

公开(公告)号：US07423319B2

公开(公告)日：2008-09-09

申请号：US11646683

申请日：2006-12-28

申请人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

发明人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66659

摘要： A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.