公开(公告)号：US06140862A

公开(公告)日：2000-10-31

申请号：US129387

申请日：1998-08-05

申请人： Tsukasa Hagura

发明人： Tsukasa Hagura

IPC分类号： G11C11/407 ,  G05F1/46 ,  G05F3/24 ,  G05F3/26 ,  G11C5/14 ,  G05F3/02

CPC分类号： G05F1/465 ,  G11C5/147 ,  G05F3/262

摘要： A semiconductor integrated circuit has an internal power supply circuit which includes a differential amplifier, a driver transistor having its gate connected to an output terminal of the differential amplifier and is connected between an external power supply node and an internal power supply node, four transistors connected in parallel between the internal power supply node and a non-inversion input terminal of the differential amplifier, a first control circuit provided corresponding to two of the four transistors, and a second control circuit provided corresponding to remaining two of the transistors. The first control circuit includes a first fuse and a first signal generating circuit. The first signal generating circuit outputs a low level first control signal to the gate of the corresponding transistor when a first fuse is disconnected, and outputs a high level first control signal to the gate of the corresponding transistor when the first fuse is connected. The second control circuit includes a second fuse and a second signal generating circuit. The second signal generating circuit outputs a high level second control signal to the gate of the corresponding transistor when the second fuse is disconnected, and outputs a low level second control signal to the gate of the corresponding transistor when the second fuse is connected.

摘要翻译： 半导体集成电路具有内部电源电路，该内部电源电路包括差分放大器，其栅极连接到差分放大器的输出端并连接在外部电源节点和内部电源节点之间的驱动晶体管，四个晶体管连接 在所述内部电源节点和所述差分放大器的非反相输入端子之间并联设置对应于所述四个晶体管中的两个提供的第一控制电路，以及与所述晶体管中剩余的两个晶体管相对应地设置的第二控制电路。 第一控制电路包括第一熔丝和第一信号发生电路。 当第一熔丝断开时，第一信号发生电路将低电平第一控制信号输出到相应晶体管的栅极，并且当第一熔丝连接时，将高电平第一控制信号输出到相应晶体管的栅极。 第二控制电路包括第二熔丝和第二信号发生电路。 当第二熔丝断开时，第二信号发生电路向相应晶体管的栅极输出高电平的第二控制信号，并且当连接第二熔丝时，将低电平的第二控制信号输出到相应晶体管的栅极。

公开(公告)号：US06693838B2

公开(公告)日：2004-02-17

申请号：US10267753

申请日：2002-10-10

申请人： Tsukasa Hagura ,  Takafumi Takatsuka ,  Masaki Tsukude

发明人： Tsukasa Hagura ,  Takafumi Takatsuka ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.

摘要翻译： 诸如伪SRAM等的半导体存储器件设置有根据具有预定刷新周期并由刷新定时信号发生器电路产生的刷新定时信号进行刷新的存储单元阵列。 选择器根据预定的命令信号选择块以将数据保存在被划分成多个块的数据中，并且信号发生器根据由所述选择装置选择的块的数量来改变刷新周期，并且生成 刷新定时信号具有改变的刷新周期并输出产生的刷新信号。

公开(公告)号：US06717878B2

公开(公告)日：2004-04-06

申请号：US10263088

申请日：2002-10-03

申请人： Tsukasa Hagura ,  Masaki Tsukude

发明人： Tsukasa Hagura ,  Masaki Tsukude

IPC分类号： G11C704

CPC分类号： G11C7/04 ,  G11C11/406

摘要： A first reference current having a first temperature characteristic is generated by a first reference current generating circuit (1) while a second reference current having a second temperature characteristic is generated by a second reference current generating circuit (2). A temperature characteristic multiplying circuit (3) amplifies the first reference current by using a current difference between the first and second reference currents to generate a reference current having a third temperature characteristic higher than the first temperature characteristic, so that a ring oscillator (X) determines a refresh period on the basis of the reference current.

摘要翻译： 具有第一温度特性的第一参考电流由第一参考电流产生电路（1）产生，而具有第二温度特性的第二参考电流由第二参考电流产生电路（2）产生。 温度特性乘法电路（3）通过使用第一和第二参考电流之间的电流差放大第一参考电流，以产生具有高于第一温度特性的第三温度特性的参考电流，使得环形振荡器（X） 基于参考电流确定刷新周期。

公开(公告)号：US5341340A

公开(公告)日：1994-08-23

申请号：US38955

申请日：1993-03-29

申请人： Tsukasa Hagura

发明人： Tsukasa Hagura

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C5/146

摘要： A substrate bias generating circuit includes V.sub.BB generating circuits and a switching circuit. The switching circuit, in the standby period, applies an internal power supply voltage applied by an internal voltage down converting circuit to the V.sub.BB generating circuits. The switching circuit, in the active period, applies an external power supply voltage to the V.sub.BB generating circuits.

摘要翻译： 衬底偏置产生电路包括VBB发生电路和开关电路。 在待机期间，开关电路将由内部降压转换电路施加的内部电源电压施加到VBB发电电路。 开关电路在有效期内，向VBB发电电路施加外部电源电压。