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    Heterogeneous processor architecture for integrating CNN and RNN into single high-performance, low-power chip
    1.
    发明授权
    Heterogeneous processor architecture for integrating CNN and RNN into single high-performance, low-power chip 有权

    公开(公告)号：US11263515B2

    公开(公告)日：2022-03-01

    申请号：US15888102

    申请日：2018-02-05

    Applicant: UX FACTORY CO., LTD. ,  Dongjoo Shin

    Inventor： Dongjoo Shin ,  Jinmook Lee ,  Jinsu Lee ,  Ju Hyoung Lee

    IPC: G06N3/08 ,  G06N3/04

    Abstract: A heterogeneous processor architecture for integrating a convolutional neural network (CNN) and a recurrent neural network (RNN) into a single high-performance, low-power chip in a neural network processor architecture, the heterogeneous processor architecture includes: an on-chip integrated circuit including a CNN operator for processing the CNN, an RNN operator for processing the RNN, an operation controller for performing control, a memory for storing data which is to be used by the operators, an interface for externally exchanging data, and a data bus through which data moves between constituent elements, wherein a fully-connected layer constituting the CNN performs data processing by sharing the RNN operator.

    SRAM STRUCTURE SUPPORTING TRANSPOSED READING
    4.
    发明申请
    SRAM STRUCTURE SUPPORTING TRANSPOSED READING 审中-公开

    公开(公告)号：US20190206483A1

    公开(公告)日：2019-07-04

    申请号：US15882983

    申请日：2018-01-29

    Applicant: UX FACTORY CO., LTD.

    Inventor： Kyeong Ryeol BONG

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/418

    Abstract: An SRAM cell is constructed by 7 transistors supporting transposed reading in addition to normal reading and writing, thereby retrieving a plurality of data through one-time reading even during column-wise parallel processing as well as row-wise parallel processing. Therefore, delay caused by multiple-time reading and increase in power consumption, occurring in a conventional SRAM, can be solved.

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