公开(公告)号：US20060214736A1

公开(公告)日：2006-09-28

申请号：US11102936

申请日：2005-03-23

申请人： Vesa Salonen ,  Sami Vilhonen

发明人： Vesa Salonen ,  Sami Vilhonen

IPC分类号： H03L7/00

CPC分类号： H03L7/189 ,  H03L7/113

摘要： A PLL comprises a VCO and a loop filter, wherein the VCO generates an AC output signal having a frequency which depends on an applied control voltage, and wherein the loop filter provides a control voltage to the VCO. The control voltage reflects determined phase differences between a potentially frequency divided output signal of the VCO and a reference signal. When operating the PLL, frequency deviations between a potentially frequency divided output signal of the VCO and a reference signal are detected and in addition, a resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. In case a frequency deviation is detected, a direct-current voltage shift is added to the control voltage provided by the loop filter.

摘要翻译： PLL包括VCO和环路滤波器，其中VCO产生具有取决于施加的控制电压的频率的AC输出信号，并且其中环路滤波器向VCO提供控制电压。 控制电压反映了VCO的潜在分频输出信号与参考信号之间确定的相位差。 当操作PLL时，检测VCO的潜在分频输出信号与参考信号之间的频率偏差，此外，用于检测频率偏差的分辨率低于用于确定相位差的分辨率。 在检测到频率偏差的情况下，将直流电压偏移加到由环路滤波器提供的控制电压。

公开(公告)号：US06597352B1

公开(公告)日：2003-07-22

申请号：US09305525

申请日：1999-05-05

申请人： Hannu Haapakoski ,  Vesa Salonen ,  Kari Vigelius

发明人： Hannu Haapakoski ,  Vesa Salonen ,  Kari Vigelius

IPC分类号： G09G500

CPC分类号： G09G5/006 ,  G09G5/18 ,  H04N5/10

摘要： A method and a device for filtered sync signals detection wherein a timing circuit is used to select the steep slope portion in one or both of the leading edge and the trailing edge of the sync signals; a voltage divider or feedback path to set a triggering point at the steep slope portion of the selected edge regardless the slope being positive or negative; and a triggerable device is used to generate new sync signals with the leading edge of each sync pulse starts at one triggering point and the trailing edge starts at another triggering point. Alternatively, a micro-controller is used to detect the polarity of the sync signals and accordingly provide a reference voltage in order to set the triggering point at the leading edge of the sync signals.

摘要翻译： 一种用于滤波同步信号检测的方法和装置，其中使用定时电路来选择同步信号的前沿和后沿中的一个或两个中的陡峭斜率部分; 分压器或反馈路径，用于在所选边缘的陡坡部分设置触发点，而不管斜率为正或负; 并且可触发装置用于产生新的同步信号，每个同步脉冲的前沿从一个触发点开始，并且后沿从另一个触发点开始。 或者，微控制器用于检测同步信号的极性，并因此提供参考电压，以便将触发点设置在同步信号的前沿。

公开(公告)号：US07321267B2

公开(公告)日：2008-01-22

申请号：US11102936

申请日：2005-03-23

申请人： Vesa Salonen ,  Sami Vilhonen

发明人： Vesa Salonen ,  Sami Vilhonen

IPC分类号： H03L7/087

CPC分类号： H03L7/189 ,  H03L7/113

摘要： A PLL comprises a VCO and a loop filter, wherein the VCO generates an AC output signal having a frequency which depends on an applied control voltage, and wherein the loop filter provides a control voltage to the VCO. The control voltage reflects determined phase differences between a potentially frequency divided output signal of the VCO and a reference signal. When operating the PLL, frequency deviations between a potentially frequency divided output signal of the VCO and a reference signal are detected and in addition, a resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. In case a frequency deviation is detected, a direct-current voltage shift is added to the control voltage provided by the loop filter.

摘要翻译： PLL包括VCO和环路滤波器，其中VCO产生具有取决于施加的控制电压的频率的AC输出信号，并且其中环路滤波器向VCO提供控制电压。 控制电压反映了VCO的潜在分频输出信号与参考信号之间确定的相位差。 当操作PLL时，检测VCO的潜在分频输出信号与参考信号之间的频率偏差，此外，用于检测频率偏差的分辨率低于用于确定相位差的分辨率。 在检测到频率偏差的情况下，将直流电压偏移加到由环路滤波器提供的控制电压。