公开(公告)号：US07463061B1

公开(公告)日：2008-12-09

申请号：US11185426

申请日：2005-07-19

申请人： Jonathan W. Greene ,  Vidya Bellippady

发明人： Jonathan W. Greene ,  Vidya Bellippady

IPC分类号： H03K19/20

CPC分类号： H03K19/0008

摘要： A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than VCC present on it.

摘要翻译： 减少泄漏的互连电路包括具有输入和输出的缓冲器，耦合在多路复用器输入节点和缓冲器的输入之间的至少一个多路复用器晶体管，以及耦合在固定状态多路复用器输入节点 以及缓冲器的输入，固定状态多路复用器输入节点具有小于零伏特或高于其上存在的VCC的电位。

公开(公告)号：US20050190626A1

公开(公告)日：2005-09-01

申请号：US11113286

申请日：2005-04-21

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

公开(公告)号：US06891769B2

公开(公告)日：2005-05-10

申请号：US10623111

申请日：2003-07-17

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

公开(公告)号：US20050013186A1

公开(公告)日：2005-01-20

申请号：US10623111

申请日：2003-07-17

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

摘要翻译： 用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。 刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。 开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。 地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

公开(公告)号：US07120079B2

公开(公告)日：2006-10-10

申请号：US11113286

申请日：2005-04-21

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

公开(公告)号：US20080279028A1

公开(公告)日：2008-11-13

申请号：US12181969

申请日：2008-07-29

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C7/00

CPC分类号： G11C11/406

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

摘要翻译： 用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。 刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。 开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。 地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

公开(公告)号：US07187610B1

公开(公告)日：2007-03-06

申请号：US11484244

申请日：2006-07-10

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/404 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4093 ,  G11C14/00 ,  G11C14/0018 ,  G11C16/0441 ,  G11C16/3431

摘要： A method for providing a circuit for selectively interconnecting N pairs of nodes in an integrated circuit device comprising: providing a memory array having a plurality of wordlines and a plurality of bitlines; providing a plurality of dynamic random access memory wordlines; providing a separate switch for each pair of nodes in the integrated circuit, each switch associated with a unique combination of one of the plurality of bitlines and one of the plurality of dynamic random access memory wordlines, each switch including a refresh transistor and a switching transistor; and providing an address decoder having at least N distinct states for supplying signals to the plurality of wordlines and the plurality of dynamic random access memory wordlines.

摘要翻译： 一种用于提供用于选择性地互连集成电路设备中的N对节点的电路的方法，包括：提供具有多个字线和多个位线的存储器阵列; 提供多个动态随机存取存储器字线; 为集成电路中的每对节点提供单独的开关，每个开关与多个位线之一和多个动态随机存取存储器字线之一的唯一组合相关联，每个开关包括刷新晶体管和开关晶体管 ; 以及提供具有至少N个不同状态的地址解码器，用于向多个字线和多个动态随机存取存储器字线提供信号。

公开(公告)号：US07499360B2

公开(公告)日：2009-03-03

申请号：US11619547

申请日：2007-01-03

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4093 ,  G11C14/00 ,  G11C14/0018 ,  G11C16/0441 ,  G11C16/3431

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

摘要翻译： 用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。 刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。 开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。 地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

公开(公告)号：US20070104009A1

公开(公告)日：2007-05-10

申请号：US11619547

申请日：2007-01-03

申请人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

发明人： John McCollum ,  Vidya Bellippady ,  Gregory Bakker

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C11/4093 ,  G11C14/00 ,  G11C14/0018 ,  G11C16/0441 ,  G11C16/3431

摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.

摘要翻译： 用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。 刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。 开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。 地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。