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公开(公告)号：US20240355397A1
公开(公告)日：2024-10-24
申请号：US18762228
申请日：2024-07-02
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/28 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3459
摘要： Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.
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2.发明授权公开(公告)号：US12112813B2
公开(公告)日：2024-10-08
申请号：US17847056
申请日：2022-06-22
发明人： Sunyoung Jo , Jungwuk Park , Younghyun Park , Sang Ho Yun , Jaekyun Moon
CPC分类号： G11C16/3431 , G06N3/045 , G11C16/28
摘要： A device includes a threshold voltage distribution estimation network configured to generate an estimated distribution using a feature distribution and read trial information, a set of feature distributions generated from a plurality of threshold voltage distributions for a plurality of pages of a memory device, and a read reference voltage estimation network configured to generate a read reference voltage from the estimated distribution. The read trial information includes a read trial vector and an output value, the output value being generated by applying the read trial vector to a threshold voltage distribution for a page to be read among the plurality of threshold voltage distributions.
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公开(公告)号：US12057174B2
公开(公告)日：2024-08-06
申请号：US17669073
申请日：2022-02-10
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/28 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3459
摘要： Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.
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公开(公告)号：US12020758B2
公开(公告)日：2024-06-25
申请号：US17318597
申请日：2021-05-12
发明人： Kun-Woo Song , Jonghwa Kim , Kyungyong Jeoung
CPC分类号： G11C16/3431 , G11C16/0483 , G11C16/34 , G11C16/10 , G11C16/26 , H10B43/27
摘要： Disclosed is a storage device, which includes a nonvolatile memory device including a first memory block connected with a plurality of first word lines, and a memory controller connected with the nonvolatile memory device through a plurality of data lines. The memory controller sends a first command to the nonvolatile memory device through the plurality of data lines during a first command input period, sends a parameter to the nonvolatile memory device through the plurality of data lines during an address input period, and sends a second command to the nonvolatile memory device through the plurality of data lines during a second command input period. The nonvolatile memory device applies a turn-on voltage to all the plurality of first word lines connected with the first memory block based on the parameter during a first time in response to the first command and the second command.
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5.发明公开公开(公告)号：US20240161838A1
公开(公告)日：2024-05-16
申请号：US18505855
申请日：2023-11-09
发明人： Nicola Ciocchini , Animesh Roy Chowdhury , Kishore Kumar Muchherla , Akira Goda , Jung Sheng Hoei , Niccolo’ Righetti , Jonathan S. Parry , Ugo Russo
CPC分类号： G11C16/3431 , G11C7/04 , G11C16/32
摘要： A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.
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公开(公告)号：US11854623B2
公开(公告)日：2023-12-26
申请号：US17520276
申请日：2021-11-05
发明人： Jaeduk Yu , Dongkyo Shim
CPC分类号： G11C16/16 , G06F3/064 , G06F12/0246 , G11C16/3431 , G11C16/3436 , G06F3/0679 , G06F2212/7211
摘要： Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.
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公开(公告)号：US11853617B2
公开(公告)日：2023-12-26
申请号：US17468588
申请日：2021-09-07
发明人： Tingjun Xie , Zhenming Zhou , Charles Kwong
CPC分类号： G06F3/0679 , G11C16/3431
摘要： A processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units; responsive to performing each write operation on a respective first memory unit of the memory device, the processing device is configured to identify a candidate memory unit that has been written to by a at least a threshold fraction of the plurality of write operations performed on the memory device; determine whether a threshold refresh criterion is satisfied; and responsive to determining that the threshold refresh criterion is satisfied, refresh data stored at one or more of the memory units that are proximate to the candidate memory unit.
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公开(公告)号：US11782627B2
公开(公告)日：2023-10-10
申请号：US17681075
申请日：2022-02-25
发明人： Kishore Kumar Muchherla , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Harish R. Singidi , Gianni S. Alsasua
CPC分类号： G06F3/0647 , G06F3/064 , G06F3/0619 , G06F3/0673 , G06F11/076 , G06F11/0727 , G06F11/0793 , G11C16/3431
摘要： A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.
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公开(公告)号：US11776640B2
公开(公告)日：2023-10-03
申请号：US17511749
申请日：2021-10-27
发明人： Kei Kitamura , Yuki Fujita , Kyosuke Matsumoto , Masahiro Kano , Minoru Yamashita , Ryuji Yamashita , Shuzo Otsuka
CPC分类号： G11C16/3431 , G06F3/0679 , G11C16/0483 , G11C16/26 , G11C16/08
摘要： A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.
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公开(公告)号：US11763899B2
公开(公告)日：2023-09-19
申请号：US17132490
申请日：2020-12-23
发明人： Jun Jun Wang , Hua Tan
CPC分类号： G11C16/3431 , G11C16/08 , G11C16/26 , G11C29/44
摘要： Methods, systems, devices, and computer-readable media for performing read disturb management of a memory device. A method includes retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.
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