公开(公告)号：US06256253B1

公开(公告)日：2001-07-03

申请号：US09507568

申请日：2000-02-18

申请人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

发明人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C8/12

摘要： An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.

摘要翻译： 集成存储器包括多个数据线和与每个数据线相关联的多个解码器。 每个数据线可以寻址单个存储器单元或多个存储器单元。 此外，每个数据线可以是存储器的字线或位线。 每个解码器在接收到其相关联的地址信号时产生使能信号。 提供具有两个输入和与每条数据线相关联的输出的多路复用器。 每个解码器的使能信号被提供给相关联的多路复用器的第一输入和与下一较高寻址数据线相关联的复用器的第二输入，以及用于控制所述多路复用器的控制输入。

公开(公告)号：US06512716B2

公开(公告)日：2003-01-28

申请号：US09772497

申请日：2001-01-29

申请人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

发明人： Klaus Oberlaender ,  Sabeen Randhawa ,  Vincent Rez{haeck over (a)}rd ,  Rod G. Fleck

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C8/10 ,  G11C8/12

摘要： An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.

摘要翻译： 集成存储器包括多个数据线和与每个数据线相关联的多个解码器。 每个数据线可以寻址单个存储器单元或多个存储器单元。 此外，每个数据线可以是存储器的字线或位线。 每个解码器在接收到其相关联的地址信号时产生使能信号。 提供具有两个输入和与每条数据线相关联的输出的多路复用器。 每个解码器的使能信号被提供给相关联的多路复用器的第一输入和与下一较高寻址数据线相关联的复用器的第二输入，以及用于控制所述多路复用器的控制输入。