公开(公告)号：US20240347088A1

公开(公告)日：2024-10-17

申请号：US18617019

申请日：2024-03-26

申请人： Micron Technology, Inc.

发明人： Corrado Villa

IPC分类号： G11C8/16 ,  G11C7/04 ,  G11C7/10 ,  G11C8/10 ,  G11C29/18

CPC分类号： G11C8/16 ,  G11C7/04 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/10 ,  G11C2029/1804 ,  G11C2207/2245

摘要： Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.

公开(公告)号：US12094526B2

公开(公告)日：2024-09-17

申请号：US18205530

申请日：2023-06-03

申请人： Zeno Semiconductor, Inc.

发明人： Jin-Woo Han ,  Neal Berger ,  Yuniarto Widjaja

IPC分类号： G11C11/401 ,  G11C5/06 ,  G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/04 ,  G11C16/08 ,  G11C29/50 ,  H10B12/00

CPC分类号： G11C11/4096 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/50 ,  H10B12/20 ,  G11C5/06 ,  G11C8/00 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0416 ,  G11C16/08 ,  G11C2211/4016

摘要： A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

公开(公告)号：US12068015B2

公开(公告)日：2024-08-20

申请号：US17894554

申请日：2022-08-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Gyuseong Kang ,  Hyuntaek Jung

IPC分类号： G11C8/10 ,  G11C11/16

CPC分类号： G11C11/1675 ,  G11C8/10 ,  G11C11/1655 ,  G11C11/1657

摘要： A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

公开(公告)号：US20240257891A1

公开(公告)日：2024-08-01

申请号：US18460046

申请日：2023-09-01

申请人： SK hynix Inc.

发明人： Ji Hwan PARK ,  Kyung Hoon KIM ,  Se Ra JEONG ,  Ha Jun JEONG ,  Jae Hoon CHA

IPC分类号： G11C29/12 ,  G11C7/22 ,  G11C8/10 ,  G11C29/18

CPC分类号： G11C29/12015 ,  G11C7/222 ,  G11C8/10 ,  G11C29/18

摘要： A command address control circuit includes a command decoding circuit, an error decision circuit, and a shifting circuit. The command decoding circuit detects a type of command address signal set in synchronization with a reference clock signal. The error decision circuit detects whether an error is present in the command address signal set, and generates a block signal based on the type of command address signal set and the results of the detection of an error. The shifting circuit outputs the command address signal set as an internal command address signal set based on the reference clock signal and the block signal.

公开(公告)号：US12046323B2

公开(公告)日：2024-07-23

申请号：US17741099

申请日：2022-05-10

申请人： SK hynix Inc.

发明人： Jeong Jin Hwang ,  Sung Nyou Yu ,  Min Jun Choi

IPC分类号： G11C8/10 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C8/10

摘要： A semiconductor device includes an address input circuit configured to boost a voltage level of at least one bit of a row address to generate a boosting address and to drive a signal of a first node based on other bits of the row address and the boosting address. The semiconductor device also includes a word line selection signal generation circuit configured to drive a signal of a second node based on the signal of the first node and to generate a word line selection signal for selecting a word line based on the signal of the second node.

公开(公告)号：US12040041B2

公开(公告)日：2024-07-16

申请号：US17448754

申请日：2021-09-24

申请人： Micron Technology, Inc.

发明人： Kurt D. Beigel ,  Scott E. Sills

IPC分类号： G11C5/02 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786 ,  H03K19/0948 ,  H10B63/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/44

CPC分类号： G11C5/025 ,  H01L21/308 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/66742 ,  H01L29/78642 ,  H03K19/0948 ,  H10B63/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/4401

摘要： A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting a gate electrode shared by neighboring vertical transistors thereof. A control logic assembly, a control logic device, an electronic system, a method of forming a control logic device, and a method of operating a semiconductor device are also described.

公开(公告)号：US12020739B2

公开(公告)日：2024-06-25

申请号：US18138849

申请日：2023-04-25

申请人： Samsung Electronics Co., Ltd.

发明人： Sunghye Cho ,  Kijun Lee ,  Eunae Lee

IPC分类号： G11C7/12 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/10 ,  G11C8/10

CPC分类号： G11C11/406 ,  G11C7/12 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C7/1078 ,  G11C8/10

摘要： A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

公开(公告)号：US12008068B2

公开(公告)日：2024-06-11

申请号：US18354679

申请日：2023-07-19

申请人： GSI Technology Inc.

发明人： Avidan Akerib ,  Pat Lasserre

IPC分类号： G06F17/16 ,  G06F3/06 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C15/00

CPC分类号： G06F17/16 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/067 ,  G06N3/04 ,  G06N3/08 ,  G11C7/22 ,  G11C15/00 ,  G06N3/063 ,  G11C7/1006 ,  G11C8/10

摘要： A device for in memory vector-matrix multiplication includes a memory array and in-memory logic. The memory array has at least two sections and stores a multiplier matrix. The memory array also receives and stores an input multiplicand arranged in a vector such that the operands of the vector-matrix multiplication are located on a same column of the memory array. Each of the sections is one of: a volatile memory array, a non-volatile memory array, a destructive memory array and a non-destructive memory array. The in-memory logic computes an output of the vector-matrix multiplication using the stored input vector and the stored multiplier matrix. The memory array is one of the following type of memory array: RAM, DRAM, SRAM, Re-RAM, ZRAM, MRAM and Memristor.

公开(公告)号：US20240153545A1

公开(公告)日：2024-05-09

申请号：US18415278

申请日：2024-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10

CPC分类号： G11C7/222 ,  G11C7/1039 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/2227

摘要： Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal. The latch circuit may synchronize the local word line sleep signal with the delayed clock signal such that the local word line sleep signal is prevented from turning off power to the word line driver until memory read and write operations of the memory cell are disabled by the word line clock signal.

公开(公告)号：US11923040B2

公开(公告)日：2024-03-05

申请号：US17805278

申请日：2022-06-03

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim

IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C8/18

CPC分类号： G11C7/1084 ,  G11C7/106 ,  G11C7/1057 ,  G11C7/1087 ,  G11C8/10 ,  G11C8/18

摘要： Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.