Decoding and selection circuit for a monolithic memory
    1.
    发明授权
    Decoding and selection circuit for a monolithic memory 失效
    单片存储器的解码和选择电路

    公开(公告)号:US4394752A

    公开(公告)日:1983-07-19

    申请号:US276136

    申请日:1981-06-22

    摘要: A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

    摘要翻译: 字线选择电路包括传统的肖特基二极管解码器和连接到字线的驱动晶体管。 当晶体管导通并且解码器的所有相关二极管关闭时,选择字线。 驱动晶体管的基极电流由与驱动晶体管的导通性相反的控制晶体管限定,并将选择电流施加到驱动晶体管的基极。 调节晶体管与控制晶体管形成电流镜以调节选择电流。 与调节晶体管相关联的补偿电路根据驱动晶体管因素调制调节晶体管的集电极电流。