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    Electrically switchable permanent storage
    1.
    发明授权
    Electrically switchable permanent storage 失效
    电可切换永久存储

    公开(公告)号：US4445202A

    公开(公告)日：1984-04-24

    申请号：US317669

    申请日：1981-11-02

    申请人： Volkmar Goetze ,  Ekkehard F. Miersch ,  Guenther Potz

    发明人： Volkmar Goetze ,  Ekkehard F. Miersch ,  Guenther Potz

    IPC分类号： G11C17/00 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  H03K19/177 ,  G11C13/00

    CPC分类号： G11C17/12 ,  H03K19/17712

    摘要： For read-only storages and in particular for PLA applications, improved coupling elements together with an associated personalization scheme permit the storing of at least two memory (or logic) connection patterns selectable independently of each other. Quick electrical switching between at least two functional modes in the same storage array, is also provided. One device field effect transistor (FET) cells with specific gate configurations depending on the respective personalization state are used as coupling elements. For instance, in a two-fold personalization permanent storage, the coupling elements consist of FETs with two gate sections provided one beside the other. For a connection to be established in only one of the two possible functions at the respective crosspoint, one of the gate sections is connected to the control line provided for the functional selection. The remaining gate section is connected to the associated input line. A connection in the other functional mode is provided correspondingly with only the control lines being switched. If at the respective crosspoint a connection is to be effective in both functional modes, both gate sections are jointly connected to the respective input line. By using only one common peripheral circuit, PLAs with multiple personalization properties can be made in integrated technology, with the same semiconductor area requirement as PLAs personalizable into only one functional mode.

    摘要翻译： 对于只读存储器，特别是对于PLA应用，改进的耦合元件以及相关联的个性化方案允许存储彼此独立选择的至少两个存储器（或逻辑）连接模式。 还提供了在同一存储阵列中的至少两个功能模式之间的快速电切换。 作为耦合元件，使用具有取决于相应个性化状态的特定栅极配置的一个器件场效应晶体管（FET）单元。 例如，在双重个性化永久存储器中，耦合元件由具有两个旁路提供的两个栅极部分的FET组成。 对于仅在相应交叉点处仅在两个可能功能中的一个中建立的连接，其中一个栅极部分连接到为功能选择提供的控制线。 剩余的栅极部分连接到相关的输入线。 相应地提供另一个功能模式的连接，只有控制线被切换。 如果在相应的交叉点处连接在两种功能模式下都是有效的，则两个门部分共同连接到相应的输入线。 通过仅使用一个通用外围电路，可以在集成技术中制造具有多种个性化特性的PLA，其具有与仅可一个功能模式个性化的PLA相同的半导体面积要求。

    Error detection and correction apparatus for a logic array
    2.
    发明授权
    Error detection and correction apparatus for a logic array 失效
    逻辑阵列的误差检测和校正装置

    公开(公告)号：US4418410A

    公开(公告)日：1983-11-29

    申请号：US214313

    申请日：1980-12-08

    申请人： Volkmar Goetze ,  Dieter Schuett

    发明人： Volkmar Goetze ,  Dieter Schuett

    IPC分类号： G06F11/00 ,  G06F11/08 ,  H03K19/177

    CPC分类号： G06F11/085 ,  H03K19/17708

    摘要： Error detection and correction apparatus for a programmable logic array (PLA) having AND and OR logic combinations merged therein is disclosed. The output lines from the AND and OR logic elements are coupled in such a manner that their functions form complete groups containing, if possible, all minterms. Missing minterms are added, as necessary, by special output lines or logic elements provided for that purpose to complete a group. If a minterm occurs on two or more function lines, the corresponding minterm is entered as a correction term into an error detection logic means, one of which is associated with each group of logic output lines. The error detection logic means are also utilized to test whether one, and only one, of the output lines in a grouping of function lines has a binary 1 value.Error correction signals are generated by mixed group error detection means, the inputs of which are connected to a function line of another function group. If a single error is detected, the error detection logic means for the function line groups indicate which group includes the erroneous function line. The mixed group error detection means similarly indicate, if appropriate, which of function lines of the mixed group is erroneous.

    摘要翻译： 公开了具有AND和OR逻辑组合的可编程逻辑阵列（PLA）的错误检测和校正装置。 来自AND和OR逻辑元件的输出线以这样的方式耦合，使得它们的功能形成包含所有minterms的完整组。 根据需要，通过专门的输出行或为此目的提供的逻辑元素来添加缺少的minterms来完成组。 如果在两个或更多个功能线上发生minterm，则将相应的minterm作为校正项输入到错误检测逻辑装置中，其中一个与每组逻辑输出线相关联。 误差检测逻辑装置还用于测试一组功能线中的输出线中是否只有一条具有二进制1值。 错误校正信号由混合组错误检测装置产生，其输入连接到另一个功能组的功能线。 如果检测到单个错误，则功能线组的错误检测逻辑装置指示哪个组包括错误的功能线。 混合组错误检测装置类似地指示混合组中的哪一个功能行是错误的。