公开(公告)号：US5144166A

公开(公告)日：1992-09-01

申请号：US608415

申请日：1990-11-02

申请人： Rafael C. Camarota ,  Frederick C. Furtek ,  Walford W. Ho ,  Edward H. Browder

发明人： Rafael C. Camarota ,  Frederick C. Furtek ,  Walford W. Ho ,  Edward H. Browder

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/17704

摘要： A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

摘要翻译： 一种包括单元和总线网络的可编程逻辑阵列，其中单元被布置在行和列的二维矩阵中，并且由总线网络互连。 细胞还通过细胞与其四个最近邻居之间的直接连接的二维阵列相互连接，一个在其左侧（或向西部），一个在其右侧（或向东部），一个在其上方（或 到北方）和其中一个（或南部）。 每个单元包括八个输入，八个输出，用于将八个输入复用到两个引线上的装置，以及响应于两个引线上的信号而工作以产生施加到八个输出的输出信号的逻辑装置。 总线网络包括用于阵列的每行和列的本地，转向和快速总线以及用于分配给定行或列的所述总线以形成总线段的中继器装置。 总线网络提供将数据传输到阵列的单元，而不使用单元作为单独的电线。

公开(公告)号：US5218240A

公开(公告)日：1993-06-08

申请号：US935116

申请日：1992-08-25

申请人： Rafael C. Camarota ,  Frederick C. Furtek ,  Walford W. Ho ,  Edward H. Browder

发明人： Rafael C. Camarota ,  Frederick C. Furtek ,  Walford W. Ho ,  Edward H. Browder

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17792

摘要： A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

摘要翻译： 一种包括单元和总线网络的可编程逻辑阵列，其中单元被布置在行和列的二维矩阵中，并且由总线网络互连。 细胞还通过细胞与其四个最近邻居之间的直接连接的二维阵列相互连接，一个在其左侧（或向西部），一个在其右侧（或向东部），一个在其上方（或 到北方）和其中一个（或南部）。 每个单元包括八个输入，八个输出，用于将八个输入复用到两个引线上的装置，以及响应于两个引线上的信号而工作以产生施加到八个输出的输出信号的逻辑装置。 总线网络包括用于阵列的每行和列的本地，转向和快速总线以及用于分配给定行或列的所述总线以形成总线段的中继器装置。 总线网络提供将数据传输到阵列的单元，而不使用单元作为单独的电线。

公开(公告)号：US5455525A

公开(公告)日：1995-10-03

申请号：US162678

申请日：1993-12-06

申请人： Walford W. Ho ,  Chao-Chiang Chen ,  Yuk Y. Yang

发明人： Walford W. Ho ,  Chao-Chiang Chen ,  Yuk Y. Yang

IPC分类号： H03K19/177

CPC分类号： H03K19/17792 ,  H03K19/17704

摘要： A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.

摘要翻译： 结构化逻辑阵列分为层次级别。 在最高级别（芯片级），块通过芯片总线系统互连。 块接口将每个块耦合到芯片总线系统以允许块彼此通信。 在较低级别，每个块包括扇区，每个扇区通过扇区接口耦合到块总线系统。 块总线系统将每个块中的扇区互连，以允许扇区彼此通信。 块总线系统还耦合到块接口，以允许在块总线系统和芯片总线系统之间传输信号。 在最低级别，每个扇区包括多个逻辑元件。 逻辑元件由扇区总线系统相互连接。 扇区总线系统耦合到扇区接口，以允许扇区总线系统和块总线系统之间的信号传输。