公开(公告)号：US12131795B2

公开(公告)日：2024-10-29

申请号：US17856691

申请日：2022-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Steven Michael Kientz

IPC: G11C7/04 ,  G11C16/26 ,  G11C16/34 ,  H03K19/17728

CPC classification number: G11C7/04 ,  G11C16/26 ,  G11C16/3495 ,  H03K19/17728

Abstract: A first analysis of each respective die of a multi-die memory device is performed. An equation to determine a respective temperature compensation (tempco) value for each respective die based on a number of program erase cycles (PECs) of the respective die based on the first analysis s determined. The equation for use in processing memory access requests directed to the respective die is stored. Whether to update the equation directed to the respective die based on a second analysis of the respective die is determined.

公开(公告)号：US12027491B2

公开(公告)日：2024-07-02

申请号：US17151634

申请日：2021-01-18

Applicant: iComeTrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

CPC classification number: H01L24/97 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H03K19/17708 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776

Abstract: A multi-chip package comprising: an interconnection substrate comprising an interconnection bridge embedded in the interconnection substrate, and an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection layer and the interconnection bridge, and a polymer layer between the first and second interconnection metal layers, wherein the interconnection bridge is embedded in the interconnection scheme and has sidewalls surrounded by the polymer layer; a semiconductor IC chip over the interconnection substrate and across over an edge of the interconnection bridge; a memory chip over the interconnection substrate and across over an edge of the interconnection bridge, wherein the interconnection bridge comprises a plurality of metal interconnects configured for a data bus coupling the semiconductor IC chip to the memory chip, wherein a bitwidth of the data bus between the semiconductor IC chip and the memory chip is greater than or equal to 512.

公开(公告)号：US12009307B2

公开(公告)日：2024-06-11

申请号：US17421460

申请日：2020-12-30

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Jicong Fan ,  Yanfei Zhang ,  Hua Yan

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17796

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/14211 ,  H01L2924/1424 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/37001

Abstract: The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

公开(公告)号：US11949414B2

公开(公告)日：2024-04-02

申请号：US17131215

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh Kalsi ,  Akshay Krishna Ramanathan ,  Kamlesh Pillai ,  Sreenivas Subramoney ,  Srivatsa Rangachar Srinivasa ,  Anirud Thyagharajan ,  Om Ji Omer ,  Saurabh Jain

IPC: H03K19/17728 ,  H03K19/1776

CPC classification number: H03K19/17728 ,  H03K19/1776

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve in-memory multiply and accumulate operations. An example apparatus includes a first multiplexer in a subarray of memory, the first multiplexer to receive first values representative of a column of a lookup table (LUT) including entries to represent products of four-bit numbers and return second values from an intersection of a row and the column of the LUT based on a first element of a first operand; shift and adder logic in the subarray, the shift and adder logic to shift the second values based on at least one of the first element of the first operand or a first element of a second operand; and accumulation storage in the subarray, the accumulation storage to store at least the shifted second values.

公开(公告)号：US20240063797A1

公开(公告)日：2024-02-22

申请号：US18240389

申请日：2023-08-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/17728 ,  H03K19/173 ,  H03K19/17758 ,  H03K19/17772

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17758 ,  H03K19/17772

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US11853141B2

公开(公告)日：2023-12-26

申请号：US17709484

申请日：2022-03-31

Applicant: Michael P. Joram ,  Emily E. Rabin ,  Bridgett M. Burg ,  Kyle S. Dalton ,  Steven H. Lohrey ,  Dominique K. James ,  Tyler M. Boitnott

Inventor： Michael P. Joram ,  Emily E. Rabin ,  Bridgett M. Burg ,  Kyle S. Dalton ,  Steven H. Lohrey ,  Dominique K. James ,  Tyler M. Boitnott

IPC: G06F1/3206 ,  G05B15/02 ,  G01R22/06 ,  G01R21/06 ,  H03K19/17728

CPC classification number: G06F1/3206 ,  G01R21/06 ,  G01R22/061 ,  G05B15/02 ,  H03K19/17728

Abstract: A computer implemented method is provided for monitoring and managing system electrical power usage. The method includes sensing component electrical usage, comparing the component usage against a corresponding lookup table, and adjusting the component usage so system power usage remains below an established threshold.

公开(公告)号：US20230385493A1

公开(公告)日：2023-11-30

申请号：US18325649

申请日：2023-05-30

Applicant: University of Florida Research Foundation, Incorporated

Inventor： Sandip RAY ,  Maneesh MERUGU ,  Dipal HALDER

IPC: G06F30/327 ,  G06F30/3323 ,  H03K19/17728

CPC classification number: G06F30/327 ,  G06F30/3323 ,  H03K19/17728

Abstract: Various embodiments of the present disclosure provide for redacting Network-on-Chip (NoC) functionality in a System-on-Chip (SoC). In one example, an embodiment provides for receiving a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, converting one or more routing tables related to the RTL source code with one or more configurable logic tables, replacing one or more connections related to the RTL source code with one or more programmable multiplexers, generating a transformed RTL source code for the SoC based on the one or more configurable logic tables and the one or more programmable multiplexers, and/or providing an attack-resistant obfuscated SoC based on the transformed RTL source code.

公开(公告)号：US20230251423A1

公开(公告)日：2023-08-10

申请号：US18016136

申请日：2021-07-12

Applicant: UNIVERSITAT POLITÈCNICA DE VALÈNCIA

Inventor： Daniel PÉREZ LÓPEZ ,  José CAPMANY FRANCOY ,  Prometheus DASMAHAPATRA

IPC: G02B6/12 ,  H03K19/17736 ,  H03K19/17728

CPC classification number: G02B6/12033 ,  H03K19/17736 ,  H03K19/17728 ,  G02B2006/12145

Abstract: The present invention relates to a programmable multicore photonic integrated circuit comprising at least one programmable photonic modules or cores, and/or other photonic units like specific high performance blocks, capable of implementing multipurpose signal processing, by the appropriate programming of its resources, routing within the circuits and the blocks to achieve multifunctional operation and the selection of its input and output ports. The invention also relates to a scalable programmable photonic integrated circuits arranged in a modular multicore approach to increase the processing power of the overall system and/or adding a multitude of functionalities enabled by complex photonics circuitry and parallelization as well as the related operation methods.

公开(公告)号：US11711082B2

公开(公告)日：2023-07-25

申请号：US17497968

申请日：2021-10-10

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H03K19/1776 ,  H01L27/22 ,  G11C11/16 ,  H03K19/0948 ,  H01L25/18 ,  G11C11/412 ,  H01L23/538 ,  H01L23/00 ,  G11C11/419 ,  H03K19/20 ,  H03K19/173 ,  G11C13/00 ,  G11C14/00 ,  H03K19/17728 ,  H01L23/498 ,  H10B10/00 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00 ,  H03K19/21

CPC classification number: H03K19/1776 ,  G11C11/1673 ,  G11C11/412 ,  G11C11/419 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C14/009 ,  G11C14/0081 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B10/15 ,  H10B61/00 ,  H10B61/10 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  G11C2213/15 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/83104 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H03K19/21 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014

Abstract: A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64.

公开(公告)号：US11683038B1

公开(公告)日：2023-06-20

申请号：US17350639

申请日：2021-06-17

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Jaideep Dastidar ,  Brian C. Gaide ,  Juan J. Noguera Serra ,  Ian A. Swarbrick

IPC: H03K19/17728 ,  H03K19/17736 ,  H03K19/17704

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/17712

Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.