公开(公告)号：US06658578B1

公开(公告)日：2003-12-02

申请号：US09410977

申请日：1999-10-01

申请人： Gilbert Laurenti ,  Jean-Pierre Giacalone ,  Emmanuel Ego ,  Anne Lombardot ,  Francois Theodorou ,  Gael Clave ,  Yves Masse ,  Karim Djafarian ,  Armelle Laine ,  Jean-Louis Tardieux ,  Eric Ponsot ,  Herve Catan ,  Vincent Gillet ,  Mark Buser ,  Jean-Marc Bachot ,  Eric Badi ,  N. M. Ganesh ,  Walter A. Jackson ,  Jack Rosenzweig ,  Shigeshi Abiko ,  Douglas E. Deao ,  Frederic Nidegger ,  Marc Couvrat ,  Alain Boyadjian ,  Laurent Ichard ,  David Russell

发明人： Gilbert Laurenti ,  Jean-Pierre Giacalone ,  Emmanuel Ego ,  Anne Lombardot ,  Francois Theodorou ,  Gael Clave ,  Yves Masse ,  Karim Djafarian ,  Armelle Laine ,  Jean-Louis Tardieux ,  Eric Ponsot ,  Herve Catan ,  Vincent Gillet ,  Mark Buser ,  Jean-Marc Bachot ,  Eric Badi ,  N. M. Ganesh ,  Walter A. Jackson ,  Jack Rosenzweig ,  Shigeshi Abiko ,  Douglas E. Deao ,  Frederic Nidegger ,  Marc Couvrat ,  Alain Boyadjian ,  Laurent Ichard ,  David Russell

IPC分类号： G06F132

CPC分类号： G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30083 ,  G06F9/3013 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/325 ,  G06F9/3552 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/3891 ,  G06K13/0825

摘要： A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

摘要翻译： 提供了具有可变指令长度的可编程固定点数字信号处理器（DSP）的处理器（100），提供高代码密度和易于编程。 架构和指令集针对低功耗和高效率执行DSP算法进行了优化，如无线电话以及纯控制任务。 处理器包括指令缓冲器单元（106），程序流控制单元（108），地址/数据流单元（110），数据计算单元（112）和多个互连总线。 双乘法累加块提高了处理性能。 存储器接口单元（104）提供对数据和指令存储器的并行访问。 指令缓冲器可用于在执行它之前缓冲单个和复合指令。 解码机构被配置为对来自指令缓冲器的指令进行解码。 使用复合指令可以有效地利用处理器内可用的带宽。 可以从单独的第一和第二编程存储器指令编译软双存储器指令。 可以有条件地执行或重复执行指令。 位场处理和各种寻址模式，如循环缓冲区寻址，进一步支持DSP算法的执行。 处理器包括具有管道保护功能的多级执行管线。 各种功能模块可以单独断电以节省电力。 处理器包括仿真和代码调试功能，支持缓存分析。

公开(公告)号：US20200340508A1

公开(公告)日：2020-10-29

申请号：US16859010

申请日：2020-04-27

申请人： Walter A. Jackson ,  Sean W. Flickinger

发明人： Walter A. Jackson ,  Sean W. Flickinger

IPC分类号： F16B2/12 ,  H04M1/04 ,  F16M11/04

摘要： A holder for holding a mobile device may include a back plate. A strut is operatively associated with the back plate so that the strut can be moved with respect to the back plate. A strut lock operatively associated with the back plate and the strut holds the back plate and strut in a desired position. A first jaw operatively associated with the back plate is sized to engage a portion of the mobile device. A second jaw sized to engage a portion of the mobile device is operatively associated with the back plate so that the second jaw can be moved toward and away from the first jaw to hold a mobile device therebetween.

公开(公告)号：US06598151B1

公开(公告)日：2003-07-22

申请号：US09411416

申请日：1999-10-01

申请人： Gilbert Laurenti ,  Walter A. Jackson ,  Jack Rosenzweig

发明人： Gilbert Laurenti ,  Walter A. Jackson ,  Jack Rosenzweig

IPC分类号： G06F948

CPC分类号： G06F7/764 ,  G06F5/01 ,  G06F7/607 ,  G06F7/74 ,  G06F7/762 ,  G06F7/78 ,  G06F9/3004 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/321

摘要： A processor (100) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region (910) is used to pass variables to a subroutine and to hold values representative of a first portion of a program counter (1000). A system stack region (911) is used to hold values representative of a remaining portion of the program counter (1001) and to hold additional context information. The user stack region and the system stack region are managed independently so that software from a prior generation processor can be translated to run on processor (100).

摘要翻译： 提供了一种具有可变指令长度的可编程数字信号处理器（DSP）的处理器（100）。 用户堆栈区域（910）用于将变量传递到子程序并保持代表程序计数器（1000）的第一部分的值。 系统堆栈区域（911）用于保存表示程序计数器（1001）的剩余部分的值并保存附加的上下文信息。 用户堆栈区域和系统堆栈区域被独立地管理，使得可以将来自上一代处理器的软件转换为在处理器（100）上运行。