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公开(公告)号：US4197470A
公开(公告)日：1980-04-08
申请号：US850525
申请日：1977-11-11
申请人： Walter H. Banzhaf
发明人： Walter H. Banzhaf
CPC分类号： H03K3/288
摘要： A triggerable bipolar flip-flop, such as an I.sup.2 L flip-flop, is comprised of a master stage, a slave stage, two logically-controlled current sources, and a clock-controlled current sink. The current source and current sink are coupled to the set and reset inputs of the master stage. When the clock signal is at one level, the current sink draws current from the set and reset inputs of the master stage, thereby disabling the master stage. When the clock signal is at a second level, the current sink turns off permitting the current source to enable the master stage. Logic signals control the current sources to selectively transmit current to the set or reset input of the master stage. Toggle, J-K, D, and pseudo D embodiments of the flip-flop may be provided.
摘要翻译： 诸如I2L触发器的可触发双极触发器由主级，从级，两个逻辑控制电流源和时钟控制的电流源组成。 电流源和电流吸收器耦合到主级的设置和复位输入。 当时钟信号处于一个电平时，电流吸收器从主级的设置和复位输入中抽取电流，从而禁用主级。 当时钟信号处于第二电平时，电流吸收器关闭，允许电流源启用主站级。 逻辑信号控制电流源以选择性地将电流传输到主级的设置或复位输入。 可以提供触发器的切换，J-K，D和伪D实施例。
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公开(公告)号：US06567971B1
公开(公告)日：2003-05-20
申请号：US10021810
申请日：2001-12-20
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method of synthesizing a circuit employs a technology parameter extraction circuit which is synthesized with constraints and simulated to derive values of performance parameters, and then, based on the derived values, a predetermined high-level circuit description of a second circuit is modified and then synthesized using the same constraints. Optional steps include the creation and substitution of a sub-circuit model to permit correct simulation, or substitution of an alternative sub-circuit to synthesize a second circuit that cannot otherwise be synthesized directly.
摘要翻译： 合成电路的方法采用技术参数提取电路，该技术参数提取电路采用约束条件合成并进行仿真，得出性能参数值，然后根据导出值修改第二电路的预定高电平电路描述， 使用相同的约束合成。 可选的步骤包括创建和替换子电路模型以允许正确的模拟，或替代替代子电路以合成否则不能直接合成的第二电路。
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