公开(公告)号：US20200174943A1

公开(公告)日：2020-06-04

申请号：US16206516

申请日：2018-11-30

申请人： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

发明人： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

IPC分类号： G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F9/38 ,  G06F11/22

摘要： In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.