公开(公告)号：US5760844A

公开(公告)日：1998-06-02

申请号：US699923

申请日：1996-08-20

申请人： William B. H. Jorden

发明人： William B. H. Jorden

IPC分类号： H03K5/007 ,  H03K5/08 ,  H04L7/10 ,  H04L25/06 ,  H04N5/08 ,  H04N5/445 ,  H04N7/035 ,  H04N5/18

CPC分类号： H04L25/062 ,  H03K5/007 ,  H03K5/082 ,  H04N5/08 ,  H04N5/44504 ,  H04N7/035 ,  H04N7/0352 ,  H04L7/10

摘要： A signal voltage level dual clamping circuit is disclosed for use in a receiving circuit for extraction of timing information from a signal. A first, start-up voltage level clamp is provided, the operation of which is independent of the signal timing information. A second, gated voltage level clamp is provided, the operation of which is dependent on the signal timing information. A switching circuit operates to switch the first clamp out of operation and switch the second clamp into operation once sufficient timing information has been extracted from the signal to permit operation of the second clamp.

摘要翻译： 公开了用于从信号中提取定时信息的接收电路中的信号电压电平双钳位电路。 提供了第一个启动电压电平钳位，其操作与信号定时信息无关。 提供第二门控电压钳位，其操作取决于信号定时信息。 一旦从信号提取足够的定时信息以允许第二夹具的操作，开关电路操作以将第一钳位开关切换到操作状态并将第二钳位切换到操作中。

公开(公告)号：US5404172A

公开(公告)日：1995-04-04

申请号：US845734

申请日：1992-03-02

申请人： Eric B. Berman ,  Apparajan Ganesan ,  William B. H. Jorden ,  Philip R. McLaughlin ,  William Posner

发明人： Eric B. Berman ,  Apparajan Ganesan ,  William B. H. Jorden ,  Philip R. McLaughlin ,  William Posner

IPC分类号： H03K5/007 ,  H03K5/08 ,  H04L7/10 ,  H04L25/06 ,  H04N5/08 ,  H04N5/445 ,  H04N7/035 ,  H04N7/087

CPC分类号： H04L25/062 ,  H03K5/007 ,  H03K5/082 ,  H04N5/08 ,  H04N5/44504 ,  H04N7/035 ,  H04N7/0352 ,  H04L7/10

摘要： A data and synchronization extraction circuit for processing composite video signals containing closed captioning data is disclosed. A dual mode voltage clamp is realized in CMOS technology which includes temperature compensated current sources in the form of complementary current mirrors. A modified version of such current sources is also disclosed which permits trimming of the current after manufacture and packaging. Sync pulses are separated by doubling the amplitude of a composite video signal with an amplifier and comparing the amplified signal with a back porch level derived by a sample-and-hold device. Frequency and phase synchronization is accomplished by a combination of a frequency lock loop and a phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator provides a clean source of timing information for the circuit. The effects of impulse noise in the detection of vertical retrace pulses are eliminated by the use of digital counting circuits which count the requisite number of horizontal synchronization pluses which occur between valid retrace pulse and which block pluses that appear at other times. A slice level for a data line is held by a small on-chip capacitor. Said slice level is periodically encoded. A decoder converts the encoded level back to an analog format during desired intervals.

摘要翻译： 公开了一种用于处理包含隐藏字幕数据的复合视频信号的数据和同步提取电路。 CMOS模式实现了双模电压钳位，其中包括补偿电流镜形式的温度补偿电流源。 还公开了这种电流源的修改版本，其允许在制造和封装之后修整电流。 通过用放大器将复合视频信号的振幅加倍来分离同步脉冲，并将放大的信号与由采样和保持设备导出的后沿电平进行比较。 频率和相位同步通过频率锁定环和相位锁相环的组合来实现，以在飞轮模式下产生用于压控振荡器的控制电压。 压控振荡器为电路提供了清晰的定时信息源。 通过使用数字计数电路来消除脉冲噪声对垂直回扫脉冲检测的影响，数字计数电路计算在有效回扫脉冲与其他时间出现的阻塞脉冲之间发生的水平同步脉冲的必要数量。 数据线的限幅电平由小的片上电容器保持。 所述切片级别被周期性地编码。 解码器将所编码的级别在期望的间隔期间转换为模拟格式。