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    DECODER AND METHOD FOR ADAPTIVELY GENERATING A CLOCK WINDOW
    2.
    发明申请
    DECODER AND METHOD FOR ADAPTIVELY GENERATING A CLOCK WINDOW 有权
    用于适应时钟生成时钟窗口的解码器和方法

    公开(公告)号：US20110164711A1

    公开(公告)日：2011-07-07

    申请号：US12651983

    申请日：2010-01-04

    申请人： TIEN-JU TSAI

    发明人： TIEN-JU TSAI

    IPC分类号： H04L7/02

    CPC分类号： H04N7/0352

    摘要： A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

    摘要翻译： 解码器和相关方法自适应地生成时钟窗口。 检测水平同步信号的下降沿，确定实际帧码与预定帧码之间的时间差。 然后，基于下降沿和时间差自适应地确定时钟窗口的开始和结束，使得可以在生成的时钟窗口内执行通过接收的时钟输入信号的符号定时恢复。

    Data signal extraction apparatus
    3.
    发明授权
    Data signal extraction apparatus 有权
    数据信号提取装置

    公开(公告)号：US07046298B2

    公开(公告)日：2006-05-16

    申请号：US10400930

    申请日：2003-03-28

    申请人： Keiichi Kuzumoto ,  Toshihiro Matsumura ,  Akihiro Suzuki ,  Atsuhisa Kageyama

    发明人： Keiichi Kuzumoto ,  Toshihiro Matsumura ,  Akihiro Suzuki ,  Atsuhisa Kageyama

    IPC分类号： H04N7/08 ,  H04N7/87 ,  H04N11/00 ,  H04N7/00

    CPC分类号： H04L7/0331 ,  H04L7/046 ,  H04N7/035 ,  H04N7/0352 ,  H04N7/0355 ,  H04N7/088

    摘要： This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.

    摘要翻译： 本发明提供一种数据信号提取装置，即使发生相移等，也能够从串行发送的数据信号中精确地提取数据。 根据该装置，相移量计算电路13计算相移量S13，然后校正量计算电路14基于相移量S13计算校正量S14，提取间隔校正电路10 基于校正量校正提取间隔值S 9，并且提取脉冲产生电路11基于校正的提取间隔值S10生成提取脉冲S 11，从而从二进制信号S 8中提取数据 提取脉冲的基础。

    Multiplexed text data sampling circuit
    5.
    发明授权
    Multiplexed text data sampling circuit 失效
    多路复用文本数据采样电路

    公开(公告)号：US5861925A

    公开(公告)日：1999-01-19

    申请号：US747012

    申请日：1996-11-07

    申请人： Shigeaki Fujitaka

    发明人： Shigeaki Fujitaka

    IPC分类号： H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08

    CPC分类号： H04N7/035 ,  H04N7/0352

    摘要： A multiplexed text data sampling circuit comprises a detecting signal inhibiting circuit (3) for inhibiting delivery of a detecting signal indicating a detection of a start bit of text broadcasting data from a start bit detecting circuit (2) during a predetermined period of time before the start bit appears, and a variable divider (71), responsive to the detecting signal, for dividing a clock signal so as to produce a sampling clock signal to sample the text broadcasting data, and for varying a dividing ratio between the frequency of the clock signal and the frequency of the sampling clock signal in such a manner that the sampling timing for each of bits of the text broadcasting except one or more last bits is adjusted so that each bit except the one or more last bits is sampled in the middle of a period of time during which each bit except the one or more last bits is applied to the sampling circuit, and the sampling timing for each of the one or more last bits is adjusted so that each bit of the one or more last bits is sampled at an earlier time of a period of time during which each bit of the one or more last bits is applied to the sampling circuit.

    摘要翻译： 复用文本数据采样电路包括检测信号禁止电路（3），用于在预定时间段之前禁止从起始位检测电路（2）发送指示检测文本广播数据的起始位的检测信号， 起始位出现，以及响应于检测信号的可变分频器（71），用于分频时钟信号，以产生采样时钟信号以对文本广播数据进行采样，并用于改变时钟频率之间的分频比 信号和采样时钟信号的频率，使得除了一个或多个最后位之外的文本广播的每个位的采样定时被调整，使得除一个或多个最后位之外的每个位在 将除一个或多个最后位之外的每个位施加到采样电路的时间段，并且调整一个或多个最后位中的每一个的采样定时，使得eac 一个或多个最后位的h位在一个或多个最后位的每个位被施加到采样电路的时间段的较早时间被采样。

    Apparatus for generating a detection clock for detecting digital data contained in a composite video signal and a data detector using detection clock
    6.
    发明授权
    Apparatus for generating a detection clock for detecting digital data contained in a composite video signal and a data detector using detection clock 失效
    用于产生用于检测包含在复合视频信号中的数字数据的检测时钟和使用检测时钟的数据检测器的装置

    公开(公告)号：US5629738A

    公开(公告)日：1997-05-13

    申请号：US480327

    申请日：1995-06-07

    申请人： Hak-sung Kim

    发明人： Hak-sung Kim

    IPC分类号： H04N7/035 ,  H04N7/087

    CPC分类号： H04N7/0355 ,  H04N7/0352

    摘要： A detection clock generating apparatus generates a detection clock signal for detecting digital data contained in the vertical blanking period of a received composite video signal. A slicer generates a slicing reference signal based on the analog clock run-in signal and slices the received analog clock run-in signal by using the generated slicing reference signal. A synchronizing portion synchronizes the sliced data with an internal clock signal. An edge detecting portion detects the rising edges of pulses of the synchronized sliced data and outputs an edge detection signal. A clock generator generates a detection clock signal on based on the pulses of the edge detection signal.

    摘要翻译： 检测时钟生成装置生成用于检测包含在接收的复合视频信号的垂直消隐期间的数字数据的检测时钟信号。 切片器基于模拟时钟输入信号生成切片参考信号，并使用生成的切片参考信号对接收的模拟时钟输入信号进行分片。 同步部分将分片数据与内部时钟信号同步。 边缘检测部分检测同步分片数据的脉冲的上升沿并输出边缘检测信号。 时钟发生器基于边缘检测信号的脉冲产生检测时钟信号。

    Closed-caption decoder circuit having robust synchronization features
    7.
    发明授权
    Closed-caption decoder circuit having robust synchronization features 失效
    具有鲁棒同步特征的闭路字幕解码器电路

    公开(公告)号：US5506626A

    公开(公告)日：1996-04-09

    申请号：US181985

    申请日：1994-01-14

    申请人： Yukihiro Yagi ,  Masayuki Nakaimuki ,  Shinichi Takahashi ,  Jeff M. Huard

    发明人： Yukihiro Yagi ,  Masayuki Nakaimuki ,  Shinichi Takahashi ,  Jeff M. Huard

    IPC分类号： H04N7/035 ,  H04N7/08

    CPC分类号： H04N7/0352

    摘要： A closed-caption decoder which uses separate clock generators to produce the sampling frequencies for the clock run-in signal and the data portion of the closed-caption signal. Each of the clock generators generates its signal from a common 12 MHz reference clock signal. The timing of the sampling clock signal for the closed-caption data is advanced at the start of the sampling interval to reduce the total timing errors in the sampling of the closed-caption data. Additionally, the decoder can adaptively select one of four edges of the clock run-in signal to use as its synchronizing reference. Furthermore, the decoder may be adapted to recognize more than one start byte pattern.

    摘要翻译： 一种封闭字幕解码器，其使用单独的时钟发生器来产生时钟输入信号和闭路字幕信号的数据部分的采样频率。 每个时钟发生器从公共12MHz参考时钟信号产生其信号。 封闭字幕数据的采样时钟信号的定时在采样间隔开始时提前，以减少闭路字幕数据采样中的总定时误差。 此外，解码器可以自适应地选择时钟输入信号的四个边沿中的一个作为其同步参考。 此外，解码器可以适于识别多于一个起始字节模式。

    Video signal data and composite synchronization extraction circuit for on-screen display
    8.
    发明授权
    Video signal data and composite synchronization extraction circuit for on-screen display 失效
    视频信号数据和复合同步提取电路，用于屏幕显示

    公开(公告)号：US5404172A

    公开(公告)日：1995-04-04

    申请号：US845734

    申请日：1992-03-02

    申请人： Eric B. Berman ,  Apparajan Ganesan ,  William B. H. Jorden ,  Philip R. McLaughlin ,  William Posner

    发明人： Eric B. Berman ,  Apparajan Ganesan ,  William B. H. Jorden ,  Philip R. McLaughlin ,  William Posner

    IPC分类号： H03K5/007 ,  H03K5/08 ,  H04L7/10 ,  H04L25/06 ,  H04N5/08 ,  H04N5/445 ,  H04N7/035 ,  H04N7/087

    CPC分类号： H04L25/062 ,  H03K5/007 ,  H03K5/082 ,  H04N5/08 ,  H04N5/44504 ,  H04N7/035 ,  H04N7/0352 ,  H04L7/10

    摘要： A data and synchronization extraction circuit for processing composite video signals containing closed captioning data is disclosed. A dual mode voltage clamp is realized in CMOS technology which includes temperature compensated current sources in the form of complementary current mirrors. A modified version of such current sources is also disclosed which permits trimming of the current after manufacture and packaging. Sync pulses are separated by doubling the amplitude of a composite video signal with an amplifier and comparing the amplified signal with a back porch level derived by a sample-and-hold device. Frequency and phase synchronization is accomplished by a combination of a frequency lock loop and a phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator provides a clean source of timing information for the circuit. The effects of impulse noise in the detection of vertical retrace pulses are eliminated by the use of digital counting circuits which count the requisite number of horizontal synchronization pluses which occur between valid retrace pulse and which block pluses that appear at other times. A slice level for a data line is held by a small on-chip capacitor. Said slice level is periodically encoded. A decoder converts the encoded level back to an analog format during desired intervals.

    摘要翻译： 公开了一种用于处理包含隐藏字幕数据的复合视频信号的数据和同步提取电路。 CMOS模式实现了双模电压钳位，其中包括补偿电流镜形式的温度补偿电流源。 还公开了这种电流源的修改版本，其允许在制造和封装之后修整电流。 通过用放大器将复合视频信号的振幅加倍来分离同步脉冲，并将放大的信号与由采样和保持设备导出的后沿电平进行比较。 频率和相位同步通过频率锁定环和相位锁相环的组合来实现，以在飞轮模式下产生用于压控振荡器的控制电压。 压控振荡器为电路提供了清晰的定时信息源。 通过使用数字计数电路来消除脉冲噪声对垂直回扫脉冲检测的影响，数字计数电路计算在有效回扫脉冲与其他时间出现的阻塞脉冲之间发生的水平同步脉冲的必要数量。 数据线的限幅电平由小的片上电容器保持。 所述切片级别被周期性地编码。 解码器将所编码的级别在期望的间隔期间转换为模拟格式。

    Sampling clock pulse generator
    9.
    发明授权
    Sampling clock pulse generator 失效
    采样时钟脉冲发生器

    公开(公告)号：US4672639A

    公开(公告)日：1987-06-09

    申请号：US736370

    申请日：1985-05-21

    申请人： Toshiyuki Tanabe ,  Minoru Noguchi

    发明人： Toshiyuki Tanabe ,  Minoru Noguchi

    IPC分类号： H04L7/033 ,  H04L7/04 ,  H04N7/035 ,  H04L7/00

    CPC分类号： H04L7/0338 ,  H04N7/0352 ,  H04L7/046

    摘要： A sampling pulse generator receives a plurality of clock signals having the same frequency and phase differences. An additional signal, which may be a clock-run-in signal is also inputted to the generator. Phase relationship data are constructed and assembled and an optimum one of the clock signals is selected and outputted based on the phase data.

    摘要翻译： 采样脉冲发生器接收具有相同频率和相位差的多个时钟信号。 可以是时钟输入信号的附加信号也被输入到发生器。 相位关系数据被构造和组合，并且基于相位数据选择和输出最佳的一个时钟信号。